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1. 发明授权

US06660600B2 Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors 有权
公开(公告)号：US06660600B2
公开(公告)日：2003-12-09
申请号：US10233020
申请日：2002-08-30
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/823425 , H01L29/41775 , H01L29/41783 , H01L29/665
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.

2. 发明授权

US06211026B1 Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors 有权
标题翻译：形成集成电路的方法，形成场效应晶体管的升高的源极/漏极区域的方法以及形成场效应晶体管的方法
公开(公告)号：US06211026B1
公开(公告)日：2001-04-03
申请号：US09203541
申请日：1998-12-01
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/823425 , H01L27/10873 , H01L29/41775 , H01L29/41783 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66545 , Y10S438/947
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.
摘要翻译：描述形成集成电路的方法，形成升高的源极/漏极区域的方法以及形成场效应晶体管的方法。在一个实施例中，在半导体衬底上形成晶体管栅极线。包含未掺杂的半导体材料的层横向地形成在晶体管栅极线附近，并与衬底的半导体材料接合并且包括用于该线的晶体管的升高的源极/漏极材料。随后，将升高的源极/漏极材料提供导电性改性杂质。在另一个实施例中，利用共同的步骤来将升高电导率的杂质提供到升高的源极/漏极材料和栅极线的材料中。在另一个实施例中，首先对未掺杂的半导体层进行图案化和蚀刻，以在提供导电性改性杂质之前提供升高的源/漏区。在另一个实施例中，半导体材料首先被图案化，其中导电性改性杂质被提供到半导体材料的选定部分。随后相对于掺杂的半导体材料部分选择性地去除未掺杂的半导体部分。

3. 发明授权

US06444529B1 Methods of forming integrated circuitry and methods of forming elevated source/drain regions of a field effect transistor 有权
公开(公告)号：US06444529B1
公开(公告)日：2002-09-03
申请号：US09771449
申请日：2001-01-26
申请人： Aftab Ahmad , Lyle Jones
发明人： Aftab Ahmad , Lyle Jones
IPC分类号： H01L21336
摘要： Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned with conductivity modifying impurity being provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions.

4. 发明授权

US07176549B2 Shallow trench isolation using low dielectric constant insulator 有权
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US07176549B2
公开(公告)日：2007-02-13
申请号：US11012012
申请日：2004-12-13
申请人： Klaus F. Schuegraf , Aftab Ahmad
发明人： Klaus F. Schuegraf , Aftab Ahmad
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

5. 发明授权

US06930363B2 Barrier in gate stack for improved gate dielectric integrity 失效
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06930363B2
公开(公告)日：2005-08-16
申请号：US10901552
申请日：2004-07-27
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

6. 发明授权

US06770571B2 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06770571B2
公开(公告)日：2004-08-03
申请号：US10339731
申请日：2003-01-08
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2131
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

7. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

8. 发明授权

US06373114B1 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06373114B1
公开(公告)日：2002-04-16
申请号：US09178306
申请日：1998-10-23
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2994
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

9. 发明授权

US06281092B1 Method for manufacturing a metal-to-metal capacitor utilizing only one masking step 有权
标题翻译：仅使用一个掩模步骤来制造金属 - 金属电容器的方法
公开(公告)号：US06281092B1
公开(公告)日：2001-08-28
申请号：US09347487
申请日：1999-07-02
申请人： Aftab Ahmad
发明人： Aftab Ahmad
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3212
摘要： A capacitor is fabricated on a semiconductor substrate by first forming a first capacitor electrode on the semiconductor substrate and forming a planar insulating layer over the first capacitor electrode. A photoresist layer is then formed over the planar insulating layer and patterned utilizing in only masking step to form an opening over the first capacitor electrode. Through the opening, the planar insulating layer is etched, and a capacitor dielectric layer is thereafter formed. A second capacitor electrode is then formed over the capacitor dielectric layer in alignment with the first capacitor electrode. The structure is planarized to expose the planar insulating layer. In a preferred embodiment, a trench in the second capacitor electrode is protected during planarization by a spin-on photoresist that is stripped following planarization.
摘要翻译：在半导体衬底上制造电容器，首先在半导体衬底上形成第一电容器电极，并在第一电容器电极上形成平面绝缘层。然后在平面绝缘层上形成光致抗蚀剂层，并且仅在掩模步骤中利用图案化以在第一电容器电极上形成开口。通过开口蚀刻平面绝缘层，然后形成电容器电介质层。然后在电容器电介质层上形成与第一电容器电极对准的第二电容器电极。将该结构平坦化以暴露平面绝缘层。在优选实施例中，第二电容器电极中的沟槽在平坦化期间通过在平坦化之后剥离的旋涂光致抗蚀剂被保护。

10. 发明授权

US6046472A Graded LDD implant process for sub-half-micron MOS devices 失效
公开(公告)号：US6046472A
公开(公告)日：2000-04-04
申请号：US949997
申请日：1997-10-14
申请人： Aftab Ahmad , Charles Dennison
发明人： Aftab Ahmad , Charles Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/784
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/823814 , H01L29/1083 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90 , Y10S257/917
摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

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