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1. 发明申请

US20080022167A1 Real-time optimized testing of semiconductor device 有权
标题翻译：半导体器件的实时优化测试
公开(公告)号：US20080022167A1
公开(公告)日：2008-01-24
申请号：US11730792
申请日：2007-04-04
申请人： Ae-yong Chung , Hwa-cheol Lee , Se-rae Cho , Kyeong-seon Shin
发明人： Ae-yong Chung , Hwa-cheol Lee , Se-rae Cho , Kyeong-seon Shin
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G01R31/318511 , G11C29/54 , G11C29/56008 , G11C2029/5002
摘要： A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.
摘要翻译：公开了一种用于测试半导体器件的方法和系统。该方法提供由多个测试项目定义的集成测试程序和由测试项目的子集定义的测试程序。通过对半导体器件的批量样品测试得出测试数据，并且计算测试项目的错误率，然后与参考数据值进行比较。基于错误率与参考数据值之间的比较，可以实时修改测试程序。

2. 发明授权

US07689876B2 Real-time optimized testing of semiconductor device 有权
标题翻译：半导体器件的实时优化测试
公开(公告)号：US07689876B2
公开(公告)日：2010-03-30
申请号：US11730792
申请日：2007-04-04
申请人： Ae-yong Chung , Hwa-cheol Lee , Se-rae Cho , Kyeong-seon Shin
发明人： Ae-yong Chung , Hwa-cheol Lee , Se-rae Cho , Kyeong-seon Shin
IPC分类号： G06F11/00 , G11C29/00 , G01R31/28 , G01R31/26 , G01V1/00 , G01V1/28
CPC分类号： G11C29/56 , G01R31/318511 , G11C29/54 , G11C29/56008 , G11C2029/5002
摘要： A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.
摘要翻译：公开了一种用于测试半导体器件的方法和系统。该方法提供由多个测试项目定义的集成测试程序和由测试项目的子集定义的测试程序。通过对半导体器件的批量样品测试得出测试数据，并且计算测试项目的错误率，然后与参考数据值进行比较。基于错误率与参考数据值之间的比较，可以实时修改测试程序。

3. 发明授权

US06960908B2 Method for electrical testing of semiconductor package that detects socket defects in real time 有权
标题翻译：实时检测插座缺陷的半导体封装的电气测试方法
公开(公告)号：US06960908B2
公开(公告)日：2005-11-01
申请号：US10824220
申请日：2004-04-13
申请人： Ae-yong Chung , Sung-Ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
发明人： Ae-yong Chung , Sung-Ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G11C29/56016 , G01R31/2893 , G01R31/2894 , G11C2029/5602
摘要： An electrical testing method for a semiconductor package for detecting defects of sockets mounted on a device under test (DUT) board is provided. A tester performs electrical test, accumulates electrical test results, and compares the accumulated results to reference values. The result of the comparison decides whether a plurality of sockets mounted on the DUT board can be used or not. The decision results are transmitted to a handler so that the socket having the defects is not used on the DUT board.
摘要翻译：提供了一种用于检测安装在被测设备（DUT）板上的插座的缺陷的半导体封装的电气测试方法。测试仪进行电气测试，累积电气测试结果，并将累积结果与参考值进行比较。比较结果决定了是否可以使用安装在DUT板上的多个插槽。决定结果被传送到处理器，以便在DUT板上不使用具有缺陷的插座。

4. 发明授权

US06922050B2 Method for testing a remnant batch of semiconductor devices 有权
标题翻译：用于测试残留批次的半导体器件的方法
公开(公告)号：US06922050B2
公开(公告)日：2005-07-26
申请号：US10835143
申请日：2004-04-28
申请人： Ae-yong Chung , Sung-ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
发明人： Ae-yong Chung , Sung-ok Kim , Jeong-ho Bang , Kyeong-seon Shin , Dae-gab Chi
IPC分类号： G01R31/26 , G01R31/01 , H01L21/66 , G01R31/02
CPC分类号： G01R31/01
摘要： A method for testing semiconductor devices includes loading a customer tray with semiconductor devices to be tested. Groups of devices are transferred from the customer tray to buffer trays for testing. The number of devices in the customer tray is checked after each transfer. If the customer tray is empty, the number of semiconductor devices in the buffer trays is counted and compared with the number of semiconductor devices that can be tested simultaneously, typically either 64 or 128. If the number of semiconductor devices in the buffer trays is greater than the tester capacity, the semiconductor devices in at least one buffer tray are tested. If the number of semiconductor devices in the buffer trays is smaller than the tester capacity, semiconductor devices that were determined to be low quality in a prior test are loaded into a buffer tray, thus testing both untested and low quality devices together.
摘要翻译：一种用于测试半导体器件的方法包括：将客户托盘加载到待测试的半导体器件上。设备组从客户托盘传输到缓冲盘进行测试。客户托盘中的设备数量在每次传输后都会被检查。如果客户托盘为空，则对缓冲托盘中的半导体器件的数量进行计数，并与可同时测试的半导体器件的数量进行比较，通常为64或128.如果缓冲托盘中的半导体器件的数量较大比测试器的容量，测试至少一个缓冲盘中的半导体器件。如果缓冲盘中的半导体器件的数量小于测试器容量，则在先前测试中被确定为低质量的半导体器件被加载到缓冲托盘中，从而同时测试未测试的和低质量的器件。

5. 发明授权

US06850450B2 Fuse box including make-link and redundant address decoder having the same, and method for repairing defective memory cell 失效
标题翻译：包括制造链路和具有相同功能的冗余地址解码器的保险丝盒以及用于修复有缺陷的存储器单元的方法
公开(公告)号：US06850450B2
公开(公告)日：2005-02-01
申请号：US10075568
申请日：2002-02-13
申请人： Kwang-kyu Bang , Kyeong-seon Shin , Sang-seok Kang , Hyen-wook Ju , Jeong-ho Bang , Ho-Jeong Choi
发明人： Kwang-kyu Bang , Kyeong-seon Shin , Sang-seok Kang , Hyen-wook Ju , Jeong-ho Bang , Ho-Jeong Choi
IPC分类号： G11C29/00 , G11C11/00
CPC分类号： G11C29/785 , G11C29/781
摘要： A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.
摘要翻译：提供包括制造链路的保险丝盒和包括保险丝盒的冗余地址解码器。优选地，保险丝盒包括多个制造链接，用于通过对应的冗余存储器单元的地址对有缺陷的正常存储器单元的地址进行编程，并且该地址是行地址或列地址。冗余地址解码器包括具有用于对缺陷单元的地址进行解码的多个制造链路的熔丝盒和冗余字线选择电路，用于响应于对应于缺陷单元的地址的冗余单元的字线进行选择从保险丝盒输出的信号。

6. 发明授权

US07671361B2 Semiconductor device including fuse focus detector, fabricating method thereof and laser repair method using the fuse focus detector 有权
标题翻译：包括保险丝聚焦检测器，其制造方法和使用熔丝焦点检测器的激光修复方法的半导体器件
公开(公告)号：US07671361B2
公开(公告)日：2010-03-02
申请号：US11434144
申请日：2006-05-16
申请人： Kwang-kyu Bang , Yong-won Lee , Kyeong-seon Shin , Hyen-wook Ju , Jeong-kyu Kim
发明人： Kwang-kyu Bang , Yong-won Lee , Kyeong-seon Shin , Hyen-wook Ju , Jeong-kyu Kim
IPC分类号： H01L23/58
CPC分类号： H01L23/544 , B23K26/351 , H01L23/5258 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.
摘要翻译：提供一种半导体器件，包括熔丝焦点检测器，其制造方法和激光修复方法。在芯片区域中，可以在第一级形成保险丝。包括第一和第二导电层的熔丝聚焦检测器可以形成在划线区域中。第一导电层可以形成在第一层，而第二导电层可以形成在不同的水平。对于激光修复方法，可以将目标区域划分为子区域。在一个选择的子区域中，可以在提供关于熔丝聚焦检测器的厚度的信息的反射光测量的方向上激光扫描熔丝聚焦检测器。使用厚度信息，可以计算所选子区域中的熔丝的聚焦偏移值。当焦点偏移值在允许范围内时，可以执行熔断器切割。

7. 发明申请

US20070126084A1 Semiconductor device including fuse focus detector, fabrication method thereof and laser repair method using the fuse detector 有权
标题翻译：包括保险丝焦点检测器，其制造方法和使用熔丝检测器的激光修复方法的半导体器件
公开(公告)号：US20070126084A1
公开(公告)日：2007-06-07
申请号：US11434144
申请日：2006-05-16
申请人： Kwang-kyu Bang , Yong-won Lee , Kyeong-seon Shin , Hyen-wook Ju , Jeong-kyu Kim
发明人： Kwang-kyu Bang , Yong-won Lee , Kyeong-seon Shin , Hyen-wook Ju , Jeong-kyu Kim
IPC分类号： H01L23/544 , H01L21/30
CPC分类号： H01L23/544 , B23K26/351 , H01L23/5258 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a fuse focus detector, a fabrication method thereof and a laser repair method. In a chip region, fuses may be formed at a first level. A fuse focus detector including first and second conductive layers may be formed in a scribe line region. The first conductive layer may be formed at the first level, while the second conductive layer may be formed at a different level. For a laser repair method, a target region may be divided into sub-regions. In one selected sub-region, the fuse focus detector may be laser scanned in a direction for a reflection light measurement providing information on a thickness of the fuse focus detector. Using the thickness information, a focus offset value of a fuse in the selected sub-region may be calculated. When the focus offset value is within an allowable range, fuse cutting may be performed.
摘要翻译：提供一种半导体器件，其包括熔丝焦点检测器，其制造方法和激光修复方法。在芯片区域中，可以在第一级形成保险丝。包括第一和第二导电层的熔丝聚焦检测器可以形成在划线区域中。第一导电层可以形成在第一层，而第二导电层可以形成在不同的水平。对于激光修复方法，可以将目标区域划分为子区域。在一个选择的子区域中，可以在提供关于熔丝聚焦检测器的厚度的信息的反射光测量的方向上激光扫描熔丝聚焦检测器。使用厚度信息，可以计算所选子区域中的熔丝的聚焦偏移值。当焦点偏移值在允许范围内时，可以执行熔断器切割。

8. 发明授权

US06861682B2 Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same 有权
标题翻译：激光连接结构能够防止上部裂纹和加宽激光束的能量窗口，以及使用其的保险丝盒
公开(公告)号：US06861682B2
公开(公告)日：2005-03-01
申请号：US10290269
申请日：2002-11-08
申请人： Jeong-ho Bang , Kyeong-seon Shin , Sang-seok Kang , Ho-jeong Choi , Hyen-wook Ju , Kwang-kyu Bang
发明人： Jeong-ho Bang , Kyeong-seon Shin , Sang-seok Kang , Ho-jeong Choi , Hyen-wook Ju , Kwang-kyu Bang
IPC分类号： G11C17/18 , G11C17/14 , G11C29/00 , G11C29/04 , H01L21/82 , H01L23/525 , H01L27/10
CPC分类号： G11C17/14 , G11C29/785 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.
摘要翻译：在半导体器件中使用的激光连接结构和使用激光连接结构的熔丝盒优选地包括以预定间隔平行定位的多个第一导电线图案，以及广泛地形成在多个第一导电线图案上的第二导电线图案，形成将所述第二导电线图案连接到所述多个第一导电线图案的孔区域。优选地，在多个第一导电线图案中的每一个上形成至少一个孔区，并且在孔区中形成通孔。

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