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1. 发明公开

US20230187617A1 Gradient-Morph LiCoO2 Single Crystals with Stabilized Energy-Density above 3400 Wh/L in Full-Cells 审中-公开
公开(公告)号：US20230187617A1
公开(公告)日：2023-06-15
申请号：US17996069
申请日：2021-04-13
申请人： Ju LI , Zhi ZHU , Yimeng HUANG , Massachusetts Institute of Technology
发明人： Ju LI , Zhi Zhu , Yimeng Huang
IPC分类号： H01M4/36 , H01M4/485 , H01M4/525 , H01M4/505
CPC分类号： H01M4/366 , H01M4/485 , H01M4/525 , H01M4/505
摘要： A cathode particle has a core and an outer layer. The core includes a lithium (Li) transition metal (M) oxide. The outer layer is disposed conformally around and substantially encloses the core. The core facilitates oxygen anion redox activity and M cation redox activity. The outer layer substantially prevents oxygen anion redox and oxygen loss in the outer layer. The outer layer of the cathode particle may have a first crystal structure. The outer layer's first crystal structure may be at least one of a layered crystal structure or a spinel crystal structure. The core of the cathode particle may have a second crystal structure that is a layered crystal structure. The core may have a single-crystalline structure. The outer layer may be LiMn0.75Ni0.25O2 or LiMn0.5Ni0.5O4.

2. 发明申请

US20200239328A1 LITHIUM TRANSITION METAL OXIDE PARTICLES HAVING LITHIUM CONCENTRATION GRADIENTS, METHODS FOR FORMING THE SAME, AND BATTERY CATHODES FORMED OF SAME 审中-公开
公开(公告)号：US20200239328A1
公开(公告)日：2020-07-30
申请号：US16687416
申请日：2019-11-18
申请人： Ju Li , Zhi Zhu
发明人： Ju Li , Zhi Zhu
IPC分类号： C01G53/00 , C01G51/00 , C01G45/12 , H01M4/131
摘要： Previous hybrid-anion and cation-redox (HACR) cathodes were limited in cycling performance by irreversible anionic redox reactions caused by the loss of anions. To overcome this limitation, a lithium (Li) transition metal (M) oxide particle is described having a Li concentration gradient. In one example, the particle includes a Li-rich core region that provides capacity and energy density due anionic and cationic contributions and a Li-poor surface region surrounding the core region to inhibit anionic activity and thus substantially reduce the loss of anions. A gradient region disposed between the core and surface regions has a Li concentration profile that varies from a first Li concentration in the core region to a second Li concentration in the surface region. A high-temperature leaching method may be used to leach LiO from a Li-rich Li1+xM1−XO2 particle, thus forming a coherent Li gradient with a stabilized layered structure.

3. 发明授权

US09143121B2 System and method of adjusting a clock signal 有权
标题翻译：调整时钟信号的系统和方法
公开(公告)号：US09143121B2
公开(公告)日：2015-09-22
申请号：US13598513
申请日：2012-08-29
申请人： Jason Gonzalez , Vannam Dang , Zhi Zhu
发明人： Jason Gonzalez , Vannam Dang , Zhi Zhu
IPC分类号： H03K3/017 , H03K7/08 , H03K5/156
CPC分类号： H03K5/1565
摘要： A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.
摘要翻译：一种方法包括在可编程缓冲器处接收输入时钟信号。该方法还包括对来自可编程缓冲器的输出信号进行滤波以产生具有电压电平的滤波信号，其中电压电平指示输出信号的占空比。该方法还包括将电压电平与参考电压进行比较。该方法还包括修改可编程缓冲器的至少一个操作参数以调整输出信号的占空比。

4. 发明授权

US08798217B2 Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection 有权
标题翻译：用于使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路
公开(公告)号：US08798217B2
公开(公告)日：2014-08-05
申请号：US12938405
申请日：2010-11-03
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04L7/0337
摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
摘要翻译：在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

5. 发明申请

US20140062559A1 SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL 有权
标题翻译：调整时钟信号的系统和方法
公开(公告)号：US20140062559A1
公开(公告)日：2014-03-06
申请号：US13598513
申请日：2012-08-29
申请人： Jason Gonzalez , Vannam Dang , Zhi Zhu
发明人： Jason Gonzalez , Vannam Dang , Zhi Zhu
IPC分类号： H03K5/156
CPC分类号： H03K5/1565
摘要： A method includes receiving an input clock signal at a programmable buffer. The method further includes filtering an output signal from the programmable buffer to generate a filtered signal having a voltage level, where the voltage level indicates a duty cycle of the output signal. The method further includes comparing the voltage level to a reference voltage. The method further includes modifying at least one operating parameter of the programmable buffer to adjust the duty cycle of the output signal.
摘要翻译：一种方法包括在可编程缓冲器处接收输入时钟信号。该方法还包括对来自可编程缓冲器的输出信号进行滤波以产生具有电压电平的滤波信号，其中电压电平指示输出信号的占空比。该方法还包括将电压电平与参考电压进行比较。该方法还包括修改可编程缓冲器的至少一个操作参数以调整输出信号的占空比。

6. 发明授权

US08542039B2 High-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications 有权
标题翻译：高速预驱动器和电压电平转换器，内置去加重HDMI传输应用
公开(公告)号：US08542039B2
公开(公告)日：2013-09-24
申请号：US13294273
申请日：2011-11-11
申请人： Miao Li , Zhi Zhu , Xiaohua Kong , Nam V. Dang
发明人： Miao Li , Zhi Zhu , Xiaohua Kong , Nam V. Dang
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018514 , H04L25/0272 , H04L25/0286
摘要： In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.
摘要翻译：在一个例子中，提供了一个高速预驱动器和电压电平转换器，内置去加重HDMI传输应用。示例性集成电路包括串行器，耦合以从串行器接收差分输入的预驱动器和驱动器。预驱动器包括全部p型金属氧化物硅（PMOS）交叉耦合电平转换器，其包括四个PMOS晶体管和两个去加重PMOS晶体管，其形成耦合到交叉耦合电平的输出的去加重抽头转换器。驱动器耦合到预驱动器输出，并被配置为从前驱动器接收差分输入。

7. 发明授权

US08527797B2 System and method of leakage control in an asynchronous system 有权
标题翻译：异步系统中的泄漏控制系统和方法
公开(公告)号：US08527797B2
公开(公告)日：2013-09-03
申请号：US11964072
申请日：2007-12-26
申请人： Xiaohua Kong , Lew G. Chua-Eoan , Sei Seung Yoon , Zhi Zhu
发明人： Xiaohua Kong , Lew G. Chua-Eoan , Sei Seung Yoon , Zhi Zhu
IPC分类号： G06F1/32
CPC分类号： H03K19/0016 , G06F9/3871
摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.
摘要翻译：公开了异步管道中泄漏控制的系统和方法。在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作阶段。

8. 发明申请

US20130191679A1 DUAL MODE CLOCK/DATA RECOVERY CIRCUIT 有权
标题翻译：双模式时钟/数据恢复电路
公开(公告)号：US20130191679A1
公开(公告)日：2013-07-25
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

9. 发明申请

US20110050334A1 Integrated Voltage Regulator with Embedded Passive Device(s) 审中-公开
标题翻译：带嵌入式无源器件的集成稳压器
公开(公告)号：US20110050334A1
公开(公告)日：2011-03-03
申请号：US12552321
申请日：2009-09-02
申请人： Yuancheng Christopher Pan , Lew G. Chua-Eoan , Zhi Zhu , Junmou Zhang
发明人： Yuancheng Christopher Pan , Lew G. Chua-Eoan , Zhi Zhu , Junmou Zhang
IPC分类号： H01L25/00
CPC分类号： H01L25/16 , H01L23/642 , H01L23/645 , H01L25/0652 , H01L2224/16225 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H02M3/00 , H05K1/0262 , H05K1/141 , H05K1/185
摘要： A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.
摘要翻译：半导体封装系统具有其中部分或完全嵌入电感器和/或电容器的封装衬底。电压调节器的有源部分安装在封装基板上，并将稳定的电压提供给也安装在封装基板上的管芯。或者，电压调节器的有源部分集成到管芯中，电压调节器将电压提供给。电压调节器与电感器和/或电容器配合以向模具提供电压。电感器可以穿过封装衬底中的通孔。对于额外的电感，通过安装封装衬底的印刷电路板中的通孔可以耦合到封装衬底中的通孔。

10. 发明申请

US20100039136A1 Gate Level Reconfigurable Magnetic Logic 有权
标题翻译：门级可重构磁逻辑
公开(公告)号：US20100039136A1
公开(公告)日：2010-02-18
申请号：US12192386
申请日：2008-08-15
申请人： Lew G. Chua-Eoan , Xiaochun Zhu , Zhi Zhu
发明人： Lew G. Chua-Eoan , Xiaochun Zhu , Zhi Zhu
IPC分类号： H03K19/173
CPC分类号： G11C11/16
摘要： A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.
摘要翻译：可再编程门逻辑并行包括多个非易失性可重新配置的基于电阻状态的存储器电路，其中电路可重新配置以实现或改变所选择的门逻辑，可配置电阻状态的存储器电路各自适于接收逻辑输入信号。与多个并行非易失性可重配置电阻状态存储电路串联的评估开关被配置为基于存储器电路的编程状态提供输出信号。传感器被配置为接收输出信号并且基于输出信号和提供给传感器的参考信号来提供逻辑输出信号。可重构逻辑可以基于使用自旋转矩传递（STT）磁性隧道结（MTJ）磁阻随机存取存储器（MRAM）作为可再编程存储器元件来实现。逻辑配置在没有电源的情况下保留。

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