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1. 发明申请

US20090172452A1 System and Method of Leakage Control in an Asynchronous System 有权
标题翻译：异步系统泄漏控制系统与方法
公开(公告)号：US20090172452A1
公开(公告)日：2009-07-02
申请号：US11964072
申请日：2007-12-26
申请人： Xiaohua Kong , Lew G. Chua-Eoan , Sei Seung Yoon , Zhi Zhu
发明人： Xiaohua Kong , Lew G. Chua-Eoan , Sei Seung Yoon , Zhi Zhu
IPC分类号： G06F1/26
CPC分类号： H03K19/0016 , G06F9/3871
摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.
摘要翻译：公开了异步管道中泄漏控制的系统和方法。在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作阶段。

2. 发明授权

US08527797B2 System and method of leakage control in an asynchronous system 有权
标题翻译：异步系统中的泄漏控制系统和方法
公开(公告)号：US08527797B2
公开(公告)日：2013-09-03
申请号：US11964072
申请日：2007-12-26
申请人： Xiaohua Kong , Lew G. Chua-Eoan , Sei Seung Yoon , Zhi Zhu
发明人： Xiaohua Kong , Lew G. Chua-Eoan , Sei Seung Yoon , Zhi Zhu
IPC分类号： G06F1/32
CPC分类号： H03K19/0016 , G06F9/3871
摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.
摘要翻译：公开了异步管道中泄漏控制的系统和方法。在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作阶段。

3. 发明申请

US20120218005A1 Semiconductor Device Having On-Chip Voltage Regulator 有权
标题翻译：具有片上稳压器的半导体器件
公开(公告)号：US20120218005A1
公开(公告)日：2012-08-30
申请号：US13034845
申请日：2011-02-25
申请人： Lew G. Chua-Eoan , Charles Matar , Matthew L. Severson , Xiaohua Kong
发明人： Lew G. Chua-Eoan , Charles Matar , Matthew L. Severson , Xiaohua Kong
IPC分类号： G05F1/10 , H03B21/00
CPC分类号： G06F1/26 , G06F1/3296 , H03K19/0016 , Y02D10/172
摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.
摘要翻译：公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。半导体器件包括位于接地总线和电源总线之间的电路。电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。监视器位于接地总线和电源总线之间。监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

4. 发明申请

US20100321102A1 Leakage Reduction in Electronic Circuits 有权
标题翻译：电子线路漏电减少
公开(公告)号：US20100321102A1
公开(公告)日：2010-12-23
申请号：US12486159
申请日：2009-06-17
申请人： Xiaohua Kong , Lew G. Chua-Eoan
发明人： Xiaohua Kong , Lew G. Chua-Eoan
IPC分类号： G05F1/10
CPC分类号： H03K19/0013 , H03K19/0016
摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.
摘要翻译：在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

5. 发明申请

US20110193589A1 On-Chip Sensor For Measuring Dynamic Power Supply Noise Of The Semiconductor Chip 有权
标题翻译：用于测量半导体芯片的动态电源噪声的片上传感器
公开(公告)号：US20110193589A1
公开(公告)日：2011-08-11
申请号：US12703233
申请日：2010-02-10
申请人： Lew G. Chua-Eoan , Boris Andreev , Christopher Phan , Amirali Shayan , Xiaohua Kong , Mikhail Popovich , Mauricio Calle , IK-Joon Chang
发明人： Lew G. Chua-Eoan , Boris Andreev , Christopher Phan , Amirali Shayan , Xiaohua Kong , Mikhail Popovich , Mauricio Calle , IK-Joon Chang
IPC分类号： H03K19/00 , G01R19/00
CPC分类号： G01R31/31721 , G01R29/26
摘要： An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.
摘要翻译：片上传感器测量半导体芯片上的动态电源噪声，如电压下降。采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

6. 发明授权

US08760217B2 Semiconductor device having on-chip voltage regulator 有权
标题翻译：具有片上稳压器的半导体器件
公开(公告)号：US08760217B2
公开(公告)日：2014-06-24
申请号：US13034845
申请日：2011-02-25
申请人： Lew G. Chua-Eoan , Charlie Matar , Matthew L. Severson , Xiaohua Kong
发明人： Lew G. Chua-Eoan , Charlie Matar , Matthew L. Severson , Xiaohua Kong
IPC分类号： G11C5/14
CPC分类号： G06F1/26 , G06F1/3296 , H03K19/0016 , Y02D10/172
摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.
摘要翻译：公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。半导体器件包括位于接地总线和电源总线之间的电路。电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。监视器位于接地总线和电源总线之间。监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

7. 发明授权

US07936205B2 Leakage reduction in electronic circuits 有权
标题翻译：电子线路漏电减少
公开(公告)号：US07936205B2
公开(公告)日：2011-05-03
申请号：US12486159
申请日：2009-06-17
申请人： Xiaohua Kong , Lew G. Chua-Eoan
发明人： Xiaohua Kong , Lew G. Chua-Eoan
IPC分类号： H03K3/01
CPC分类号： H03K19/0013 , H03K19/0016
摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.
摘要翻译：在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

8. 发明申请

US20130216014A1 AUTOMATIC DETECTION AND COMPENSATION OF FREQUENCY OFFSET IN POINT-TO-POINT COMMUNICATION 有权
标题翻译：点对点通信中频率偏移的自动检测和补偿
公开(公告)号：US20130216014A1
公开(公告)日：2013-08-22
申请号：US13401020
申请日：2012-02-21
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/081 , H04L7/0025 , H04L7/033
摘要： Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.
摘要翻译：自动检测和补偿点对点通信中频偏的系统和方法。突发模式时钟和数据恢复（CDR）系统包括以第一频率接收的输入数据和以第二频率工作的参考时钟。包括第一门控压控振荡器（GVCO）的主锁相环（PLL）被配置为对准参考时钟和输入数据的相位，并提供相位误差信息和恢复的时钟。第二个GVCO由恢复的时钟控制，以对输入数据进行采样。包括从第二GVCO到主PLL的反馈路径的频率对准环路被配置为使用相位误差信息来校正第一频率和第二频率之间的频率偏移。

9. 发明申请

US20120109356A1 Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection 有权
标题翻译：使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路
公开(公告)号：US20120109356A1
公开(公告)日：2012-05-03
申请号：US12938405
申请日：2010-11-03
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
IPC分类号： G01R13/02 , G06F19/00 , H03L7/06
CPC分类号： H04L7/033 , H04L7/0337
摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
摘要翻译：在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

10. 发明授权

US08839020B2 Dual mode clock/data recovery circuit 有权
标题翻译：双模时钟/数据恢复电路
公开(公告)号：US08839020B2
公开(公告)日：2014-09-16
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/04 , G06F1/12 , H03L7/00 , H04B7/212 , H04L12/28 , H04J3/06 , H04L7/00 , H04B1/16 , G06F15/16
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

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