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1. 发明授权

US08839020B2 Dual mode clock/data recovery circuit 有权
标题翻译：双模时钟/数据恢复电路
公开(公告)号：US08839020B2
公开(公告)日：2014-09-16
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/04 , G06F1/12 , H03L7/00 , H04B7/212 , H04L12/28 , H04J3/06 , H04L7/00 , H04B1/16 , G06F15/16
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

2. 发明申请

US20130191679A1 DUAL MODE CLOCK/DATA RECOVERY CIRCUIT 有权
标题翻译：双模式时钟/数据恢复电路
公开(公告)号：US20130191679A1
公开(公告)日：2013-07-25
申请号：US13420800
申请日：2012-03-15
申请人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
发明人： Jingcheng Zhuang , Nam V. Dang , Xiaohua Kong , Zhi Zhu , Tirdad Sowlati , Behnam Amelifard
IPC分类号： G06F1/24
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/091 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
摘要翻译：时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并响应于串行数据脉冲串的第一个边沿而产生复位信号。时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。相位检测器电路耦合到振荡器。相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

3. 发明申请

US20120109356A1 Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection 有权
标题翻译：使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路
公开(公告)号：US20120109356A1
公开(公告)日：2012-05-03
申请号：US12938405
申请日：2010-11-03
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
IPC分类号： G01R13/02 , G06F19/00 , H03L7/06
CPC分类号： H04L7/033 , H04L7/0337
摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
摘要翻译：在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

4. 发明授权

US08798217B2 Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection 有权
标题翻译：用于使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路
公开(公告)号：US08798217B2
公开(公告)日：2014-08-05
申请号：US12938405
申请日：2010-11-03
申请人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Zhi Zhu , Nam V. Dang , Tirdad Sowlati
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H04L7/0337
摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
摘要翻译：在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

5. 发明申请

US20130187717A1 RECEIVER EQUALIZATION CIRCUIT 审中-公开
标题翻译：接收器均衡电路
公开(公告)号：US20130187717A1
公开(公告)日：2013-07-25
申请号：US13405468
申请日：2012-02-27
申请人： Glenn A. Murphy , Nam V. Dang , Tirdad Sowlati , Xiaohua Kong
发明人： Glenn A. Murphy , Nam V. Dang , Tirdad Sowlati , Xiaohua Kong
IPC分类号： H03F3/16
CPC分类号： H03F3/3022 , H03F1/483
摘要： A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.
摘要翻译：接收机均衡电路包括具有耦合到输入信号的栅极的第一输出晶体管。接收机均衡电路还可以包括具有耦合到第一输出晶体管的漏极的漏极的第二输出晶体管。接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和漏极之间的电阻器，以向第二输出晶体管的栅极提供直流（DC）偏置。接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和输入信号源之间的馈通电容器。当输入信号的频率高于预定阈值时，馈通电容器将输入信号馈送到第二输出晶体管的栅极。馈通电容和电阻定义了信号增益放大点。

6. 发明授权

US08634510B2 Full digital bang bang frequency detector with no data pattern dependency 失效
标题翻译：全数字爆炸频率检测器，无数据模式依赖
公开(公告)号：US08634510B2
公开(公告)日：2014-01-21
申请号：US13005271
申请日：2011-01-12
申请人： Xiaohua Kong , Vannam Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Vannam Dang , Tirdad Sowlati
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/0995
摘要： A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.
摘要翻译：提供了一种没有数据模式依赖性的爆轰频率检测器。在示例中，检测器从接收的数据恢复时钟，例如具有不归零（NRZ）格式的数据。第一个爆炸相位检测器（BBPD）提供关于采样时钟和嵌入在接收数据中的时钟之间的相位差的第一阶段信息。第二BBPD提供关于嵌入在接收数据中的时钟与采样时钟的延迟版本之间的第二相位差的第二阶段信息。基于第一和第二相位差来确定采样时钟和嵌入在接收数据中的时钟之间的频率差。频率差可用于调整采样时钟的频率。锁定检测器可以耦合到BBPD输出，以确定采样时钟是否锁定在嵌入在接收数据中的时钟。

7. 发明申请

US20120177159A1 Full Digital Bang Bang Frequency Detector with No Data Pattern Dependency 失效
标题翻译：全数字砰砰频率检测器，无数据模式依赖
公开(公告)号：US20120177159A1
公开(公告)日：2012-07-12
申请号：US13005271
申请日：2011-01-12
申请人： Xiaohua Kong , Vannam Dang , Tirdad Sowlati
发明人： Xiaohua Kong , Vannam Dang , Tirdad Sowlati
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/0995
摘要： A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.
摘要翻译：提供了一种没有数据模式依赖性的爆轰频率检测器。在示例中，检测器从接收的数据恢复时钟，例如具有不归零（NRZ）格式的数据。第一个爆炸相位检测器（BBPD）提供关于采样时钟和嵌入在接收数据中的时钟之间的相位差的第一阶段信息。第二BBPD提供关于嵌入在接收数据中的时钟与采样时钟的延迟版本之间的第二相位差的第二阶段信息。基于第一和第二相位差来确定采样时钟和嵌入在接收数据中的时钟之间的频率差。频率差可用于调整采样时钟的频率。锁定检测器可以耦合到BBPD输出，以确定采样时钟是否锁定在嵌入在接收数据中的时钟。

8. 发明授权

US08570077B2 Methods and implementation of low-power power-on control circuits 有权
标题翻译：低功率上电控制电路的方法与实现
公开(公告)号：US08570077B2
公开(公告)日：2013-10-29
申请号：US12971527
申请日：2010-12-17
申请人： Chang Ki Kwon , Craig E. Borden , Steve J. Halter , Tirdad Sowlati
发明人： Chang Ki Kwon , Craig E. Borden , Steve J. Halter , Tirdad Sowlati
IPC分类号： H03L7/00
CPC分类号： H03K17/22 , G01R19/2503 , G06F1/26 , G06F1/32
摘要： Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply.
摘要翻译：公开了低功率上电控制电路的方法和实现。在特定实施例中，一种装置包括由第一电压源供电的功率检测器电路。至少一个电压电平移位装置耦合到第二电压源，并且将测试输入提供给功率检测器电路。可选的泄漏自控装置可以减少与第一电源和第二电源相关联的不想要的泄漏电流。

9. 发明授权

US07706760B2 System and method for saturation detection, correction and recovery in a polar transmitter 有权
标题翻译：用于极性发射机饱和检测，校正和恢复的系统和方法
公开(公告)号：US07706760B2
公开(公告)日：2010-04-27
申请号：US11431758
申请日：2006-05-10
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Darioush Agahi
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Darioush Agahi
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H04B1/0475 , H03F1/32 , H03F1/34 , H03F3/189 , H03F3/24 , H03F2200/438 , H03G3/3047 , H04B2001/0433
摘要： A system for saturation detection, correction and recovery in a power amplifier includes a power amplifier, a closed power control loop configured to develop a power control signal (VPC), and power control circuitry configured to reduce the power control signal if the power amplifier is operating in a saturation mode.
摘要翻译：一种用于功率放大器中的饱和度检测，校正和恢复的系统包括：功率放大器，被配置为开发功率控制信号（VPC）的闭合功率控制回路;以及功率控制电路，其被配置为如果功率放大器为在饱和模式下工作。

10. 发明授权

US07499682B2 Dual voltage regulator for a supply voltage controlled power amplifier in a closed power control loop 有权
标题翻译：双电压调节器，用于电源电压控制功率放大器，在闭合功率控制回路中
公开(公告)号：US07499682B2
公开(公告)日：2009-03-03
申请号：US11137197
申请日：2005-05-24
申请人： Dmitriy Rozenblit , Tirdad Sowlati
发明人： Dmitriy Rozenblit , Tirdad Sowlati
IPC分类号： H04B1/04
CPC分类号： H03F1/0233 , H03F1/02 , H03F1/0205 , H03F3/24 , H03F2200/207 , H03F2200/504 , H04B2001/045
摘要： A supply voltage controlled power amplifier that comprises a power amplifier, a closed power control feedback loop configured to generate a power control signal, and a dual voltage regulator coupled to the power control feedback loop, the dual voltage regulator comprising a first regulator stage and a second regulator stage, wherein the closed power control loop minimizes noise generated by the first regulator stage.
摘要翻译：一种电源电压控制功率放大器，包括功率放大器，被配置为产生功率控制信号的闭合功率控制反馈回路，以及耦合到功率控制反馈回路的双电压调节器，所述双电压调节器包括第一调节器级和第二调节器级，其中闭合功率控制回路最小化由第一调节器级产生的噪声。

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