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1. 发明申请

US20140189317A1 APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR 有权
标题翻译：混合式延迟加工器的装置和方法
公开(公告)号：US20140189317A1
公开(公告)日：2014-07-03
申请号：US13730055
申请日：2012-12-28
申请人： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
发明人： Oren Ben-Kiki , Yuval Yosef , Ilan Pardo , Dror Markovich
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30079 , G06F9/3836 , G06F9/3855 , G06F9/3861 , G06F9/3877 , G06F9/46 , G06F15/7867 , G06F15/7892 , G06F15/80
摘要： An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
摘要翻译：描述了用于在处理设备上执行延迟优化的执行逻辑和吞吐量优化的执行逻辑的装置和方法。例如，根据一个实施例的处理器包括：执行第一类型的程序代码的等待时间优化的执行逻辑; 吞吐量优化执行逻辑以执行第二类型的程序代码，其中所述第一类型的程序代码和所述第二类型的程序代码被设计用于相同的指令集架构; 识别过程中的第一类型的程序代码和第二类型的程序代码的逻辑，并且将用于执行的第一类型的程序代码分配在延迟优化的执行逻辑和第二类型的程序代码上以便在吞吐量 - 优化的执行逻辑。

2. 发明申请

US20140189332A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 有权
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20140189332A1
公开(公告)日：2014-07-03
申请号：US13729915
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the command could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands; and one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或表示无法执行命令的原因的数据; 执行逻辑以执行包括调用一个或多个加速器命令的加速器调用指令的多个指令; 以及一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令。

3. 发明申请

US20140189191A1 APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING 有权
标题翻译：用于记忆映射寄存器缓存的装置和方法
公开(公告)号：US20140189191A1
公开(公告)日：2014-07-03
申请号：US13730030
申请日：2012-12-28
申请人： Ilan Pardo , Michael Behar , Oren Ben-Kiki , Dror Markovich
发明人： Ilan Pardo , Michael Behar , Oren Ben-Kiki , Dror Markovich
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0875 , G06F12/0897 , Y02D10/13
摘要： A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.
摘要翻译：描述了一种处理器，包括：实现为级别1（L1）数据高速缓存中的寄存器文件高速缓存和架构寄存器区域的组合的架构寄存器文件，以及数据位置表（DLT），用于存储指示每个寄存器文件缓存内的架构寄存器和/或L1数据高速缓存内的体系结构寄存器区域。

4. 发明申请

US20160283237A1 INSTRUCTIONS AND LOGIC TO PROVIDE ATOMIC RANGE OPERATIONS 审中-公开
标题翻译：说明和逻辑提供原子范围操作
公开(公告)号：US20160283237A1
公开(公告)日：2016-09-29
申请号：US14671914
申请日：2015-03-27
申请人： Ilan Pardo , Oren Ben-Kiki , Arch D. Robison , Nadav Chachmon , James H. Cownie
发明人： Ilan Pardo , Oren Ben-Kiki , Arch D. Robison , Nadav Chachmon , James H. Cownie
IPC分类号： G06F9/30 , G06F9/355
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3004 , G06F9/526
摘要： Instructions and logic provide atomic range operations in a multiprocessing system. In one embodiment an atomic range modification instruction specifies an address for a set of range indices. The instruction locks access to the set of range indices and loads the range indices to check the range size. The range size is compared with a size sufficient to perform the range modification. If the range size is sufficient to perform the range modification, the range modification is performed and one or more modified range indices of the set of range indices is stored back to memory. Otherwise an error signal is set when the range size is not sufficient to perform said range modification. Access to the set of range indices is unlocked responsive to completion of the atomic range modification instruction. Embodiments may include atomic increment next instructions, add next instructions, decrement end instructions, and/or subtract end instructions.
摘要翻译：说明和逻辑在多处理系统中提供原子范围操作。在一个实施例中，原子范围修改指令指定一组范围索引的地址。该指令锁定对范围索引的访问，并加载范围索引以检查范围大小。将范围大小与足以执行范围修改的大小进行比较。如果范围大小足以进行范围修改，则执行范围修改，并且将范围索引集合中的一个或多个修改的范围索引存储回存储器。否则当范围大小不足以执行所述范围修改时，设置错误信号。响应于原子范围修改指令的完成，对范围索引集的访问被解锁。实施例可以包括原子增量下一个指令，添加下一个指令，递减结束指令和/或减去结束指令。

5. 发明申请

US20140189333A1 APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCELERATORS 审中-公开
标题翻译：用于可切换同步硬件加速器的设备和方法
公开(公告)号：US20140189333A1
公开(公告)日：2014-07-03
申请号：US13730143
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Eliezer Weissmann
发明人： Oren Ben-Kiki , Ilan Pardo , Eliezer Weissmann
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/30054 , G06F9/30189 , G06F9/3881
摘要： A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in memory, wherein prior to executing the accelerator thread, the accelerator is to lock entries in a translation lookaside buffer (TLB) associated with the accelerator thread to prevent an exception which might otherwise result.
摘要翻译：一种处理器，包括执行逻辑，以执行包括调用加速器命令的加速器调用指令的第一线程; 加速器，其响应于加速器命令执行加速器线程，加速器，用于将与加速器线程相关联的状态数据存储在存储器中的应用存储器区域中，其中在执行加速器线程之前，加速器将锁定条目转换为与加速器线程相关联的后备缓冲器（TLB），以防止否则可能导致的异常。

6. 发明授权

US09053025B2 Apparatus and method for fast failure handling of instructions 有权
标题翻译：快速故障处理指令的装置和方法
公开(公告)号：US09053025B2
公开(公告)日：2015-06-09
申请号：US13729931
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F9/38
CPC分类号： G06F11/0793 , G06F9/3842 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/1438
摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
摘要翻译：描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域域名

7. 发明申请

US20140189426A1 APPARATUS AND METHOD FOR FAST FAILURE HANDLING OF INSTRUCTIONS 有权
标题翻译：快速故障处理指令的装置和方法
公开(公告)号：US20140189426A1
公开(公告)日：2014-07-03
申请号：US13729931
申请日：2012-12-28
申请人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
发明人： Oren Ben-Kiki , Ilan Pardo , Robert Valentine
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F9/3842 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/1438
摘要： A processor is described comprising: instruction failure logic to perform a plurality of operations in response to a detected instruction execution failure, the instruction failure logic to be used for instructions which have complex failure modes and which are expected to have a failure frequency above a threshold, wherein the operations include: detecting an instruction execution failure and determining a reason for the failure; storing failure data in a destination register to indicate the failure and to specify details associated with the failure; and allowing application program code to read the failure data and responsively take one or more actions responsive to the failure, wherein the instruction failure logic performs its operations without invocation of an exception handler or switching to a low level domain on a system which employs hierarchical protection domains.
摘要翻译：描述了一种处理器，包括：响应于检测到的指令执行失败执行多个操作的指令失败逻辑，用于具有复杂故障模式并且预期具有高于阈值的故障频率的指令的指令故障逻辑其中，所述操作包括：检测指令执行失败并确定所述故障的原因; 将故障数据存储在目的地寄存器中以指示故障并指定与故障相关的细节; 并且允许应用程序代码读取故障数据并且响应于故障响应地采取一个或多个动作，其中指令失败逻辑执行其操作而不调用异常处理程序或切换到采用分级保护的系统上的低级域域名

8. 发明授权

US09268697B2 Snoop filter having centralized translation circuitry and shadow tag array 有权
标题翻译：具有集中翻译电路和阴影标签阵列的窥探滤波器
公开(公告)号：US09268697B2
公开(公告)日：2016-02-23
申请号：US13730956
申请日：2012-12-29
申请人： Ilan Pardo , Niranjan Cooray , Stanislav Shwartsman , Shlomo Raikin
发明人： Ilan Pardo , Niranjan Cooray , Stanislav Shwartsman , Shlomo Raikin
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0822 , G06F12/0831 , G06F12/1027 , G06F12/1063
摘要： A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.
摘要翻译：描述了包括多个处理核的处理器。处理器包括耦合到每个所述处理核心的互连网络。处理器包括连接到互连网络并与处理器的相干平面逻辑电路相关联的窥探滤波器逻辑电路。监听滤波器逻辑电路包含用于保存信息的电路，该信息不仅识别哪个处理核心缓存由处理核心高速缓存的特定高速缓存线，而且在处理核心的高速缓存中缓存高速缓存行被缓存。

9. 发明授权

US08689028B2 Method and apparatus to reduce idle link power in a platform 有权
标题翻译：降低平台空闲链路功率的方法和装置
公开(公告)号：US08689028B2
公开(公告)日：2014-04-01
申请号：US13175574
申请日：2011-07-01
申请人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
发明人： Paul S. Diefenbaugh , Robert E. Gough , Yuval Bachrach , Mikal C. Hunsaker , Rafi Ben-Tal , Ilan Pardo , Gideon Prat , David J. Harriman
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/325 , G06F1/3206 , G06F1/3234 , G06F1/3278 , G06F1/3287 , Y02D10/157 , Y02D10/171
摘要： A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
摘要翻译：一种降低平台空闲链路功率的方法和装置。在本发明的一个实施例中，主机及其在平台中的耦合端点各自具有低功率空闲链路状态，其允许在主机及其耦合的端点中禁用高速链路电路。这允许平台减少其空闲功率，因为在本发明的一个实施例中，主机及其耦合端点能够关闭其高速链路电路。

10. 发明授权

US08665124B2 Compression format for high bandwidth dictionary compression 有权
标题翻译：高带宽字典压缩的压缩格式
公开(公告)号：US08665124B2
公开(公告)日：2014-03-04
申请号：US13638147
申请日：2011-10-01
申请人： Ilan Pardo , Ido Y. Soffair , Dror Reif , Debendra Das Sharma , Akshay G. Pethe
发明人： Ilan Pardo , Ido Y. Soffair , Dror Reif , Debendra Das Sharma , Akshay G. Pethe
IPC分类号： H03M7/00
CPC分类号： H03M7/3059 , H03M7/3088
摘要： Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.
摘要翻译：使用基于字典的高带宽无损压缩的方法，装置和系统。具有同步和编码以支持压缩和解压缩操作的条目的一对字典通过压缩器和解压缩器的逻辑来实现。压缩器/解压缩器逻辑操作以协作的方式，包括实现相同的字典更新方案，导致相应词典中的数据被同步。字典还配置有可替换条目，并且替换策略基于通过链接传送的数据集合中的数据的匹配字节来实现。公开了用于条目替换的各种方案以及延迟字典更新技术。该技术支持使用并行操作的线速压缩和解压缩，从而实质上无延迟开销。

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