专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08766319B2 Semiconductor device with ultra thin silicide layer 有权
标题翻译：具有超薄硅化物层的半导体器件
公开(公告)号：US08766319B2
公开(公告)日：2014-07-01
申请号：US13456238
申请日：2012-04-26
申请人： Kuo-Chih Lai , Chia Chang Hsu , Nien-Ting Ho , Bor-Shyang Liao , Shu Min Huang , Min-Chung Cheng , Yu-Ru Yang
发明人： Kuo-Chih Lai , Chia Chang Hsu , Nien-Ting Ho , Bor-Shyang Liao , Shu Min Huang , Min-Chung Cheng , Yu-Ru Yang
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/76889 , H01L29/41791 , H01L29/66795
摘要： A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
摘要翻译：半导体器件的制造方法包括以下步骤。首先，提供基板，在基板上形成至少一个翅片结构，然后在翅片结构上沉积金属层以形成自对准硅化物层。在沉积金属层之后，除去金属层，但在除去金属层之前不进行RTP。然后在去除金属层之后执行RTP。

2. 发明授权

US08310012B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08310012B2
公开(公告)日：2012-11-13
申请号：US12759670
申请日：2010-04-13
申请人： Guang-Yaw Hwang , Yu-Ru Yang , Jiunn-Hsiung Liao , Pei-Yu Chou
发明人： Guang-Yaw Hwang , Yu-Ru Yang , Jiunn-Hsiung Liao , Pei-Yu Chou
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/82385 , H01L29/42372 , H01L29/4966 , H01L29/66545 , H01L29/66583 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and at least a first conductive-type metal gate formed on the gate dielectric layer. The first conductive-type metal gate includes a filling metal layer and a U-type metal layer formed between the filling metal layer and the gate dielectric layer. A topmost portion of the U-type metal layer is lower than the filling metal layer.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的栅极电介质层和形成在栅极介电层上的至少第一导电型金属栅极。第一导电型金属栅极包括在填充金属层和栅极介电层之间形成的填充金属层和U型金属层。 U型金属层的最上部比填充金属层低。

3. 发明申请

US20110254060A1 Metal Gate Structure and Fabricating Method thereof 审中-公开
标题翻译：金属门结构及其制造方法
公开(公告)号：US20110254060A1
公开(公告)日：2011-10-20
申请号：US12760782
申请日：2010-04-15
申请人： Yu-Ru YANG , Tzung-Ying Lee , Chin-Fu Lin , Chi-Mao Hsu
发明人： Yu-Ru YANG , Tzung-Ying Lee , Chin-Fu Lin , Chi-Mao Hsu
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/518 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/665 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a metal gate structure is provided. Firstly, a high-K gate dielectric layer is formed on a semiconductor substrate. Then, a first metal-containing layer having a surface away from the gate dielectric layer is formed on the gate dielectric layer. After that, the surface of the first metal-containing layer is treated to improve the nitrogen content thereof of the surface. Subsequently, a silicon layer is formed on the first metal-containing layer. Because the silicon layer is formed on the surface having high nitrogen content, the catalyzing effect to the silicon layer resulted from the metal material in the first metal-containing layer can be prevented. As a result, the process yield is improved.
摘要翻译：提供一种制造金属栅极结构的方法。首先，在半导体衬底上形成高K栅介质层。然后，在栅极电介质层上形成具有离开栅极电介质层的表面的第一含金属层。之后，处理第一含金属层的表面以改善其表面的氮含量。随后，在第一含金属层上形成硅层。由于在具有高氮含量的表面上形成硅层，所以可以防止由第一含金属层中的金属材料产生的对硅层的催化作用。结果，工艺产量提高。

4. 发明申请

US20050098892A1 Structure and process of metal interconnects 审中-公开
标题翻译：金属互连的结构和工艺
公开(公告)号：US20050098892A1
公开(公告)日：2005-05-12
申请号：US10718897
申请日：2003-11-20
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76886 , H01L21/76805 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.
摘要翻译：提供金属互连的工艺和由其制造的金属互连结构。在电介质层中形成开口。在填充开口的电介质层上形成金属层。在金属层和电介质层上形成膜层。在热处理期间，膜层与金属层反应，在金属层的表面形成保护层。除去与金属层不反应的膜层的部分，以避免金属层之间的短路。保护层可以保护金属层的表面免受氧化，从而可以有效地促进半导体器件的稳定性和可靠性。

5. 发明申请

US20100072622A1 Method for forming Barrier Layer and the Related Damascene Structure 审中-公开
标题翻译：形成阻挡层和相关的大马士革结构的方法
公开(公告)号：US20100072622A1
公开(公告)日：2010-03-25
申请号：US12626925
申请日：2009-11-29
申请人： Yu-Ru YANG , Chien-Chung HUANG
发明人： Yu-Ru YANG , Chien-Chung HUANG
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/2855 , H01L21/76844 , H01L21/76846
摘要： A method for forming barrier layers comprises steps of forming a first metal barrier layer covering a first dielectric layer and contacting a conductive layer through a via of the first dielectric layer, forming a barrier layer of metalized materials on the first metal layer, optionally forming a second metal barrier layer on the barrier layer of metalized materials, removing portions of the barrier layer of metalized materials above the via bottom in the first dielectric layer, and leaving the barrier layer of metalized materials remaining on the via sidewall in the first dielectric layer; and forming a second metal layer covering the barrier layer of metalized materials. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：形成阻挡层的方法包括以下步骤：形成覆盖第一介电层的第一金属阻挡层，并通过第一介电层的通孔接触导电层，在第一金属层上形成金属化材料的阻挡层，任选地形成在金属化材料的阻挡层上的第二金属阻挡层，去除第一介电层中的通孔底部上方的金属化材料的阻挡层的部分，并留下金属化材料的阻挡层留在第一介电层中的通孔侧壁上; 以及形成覆盖金属化材料的阻挡层的第二金属层。完成的阻挡层在第一介电层中的通孔底部具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

6. 发明申请

US20090225490A1 CAPACITOR STRUCTURE 审中-公开
标题翻译：电容结构
公开(公告)号：US20090225490A1
公开(公告)日：2009-09-10
申请号：US12043135
申请日：2008-03-06
申请人： Tsuoe-Hsiang Liao , Huo-Tieh Lu , Yu-Fang Chien , Chih-Chien Liu , Pei-Lin Kuo , Yu-Ru Yang
发明人： Tsuoe-Hsiang Liao , Huo-Tieh Lu , Yu-Fang Chien , Chih-Chien Liu , Pei-Lin Kuo , Yu-Ru Yang
IPC分类号： H01G4/005 , H01G4/00
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01G4/33 , H01L23/5222 , H01L27/0207 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A capacitor structure has a first electrode and a second electrode, which does not electrically connect to the first electrode. The first electrode has a plurality of first meshed conductive structures. The first meshed conductive structures have the same layout pattern, and are electrically connected to each other. The second electrode has a plurality of second meshed conductive structures. The second meshed conductive structures have the same layout pattern, and are electrically connected to each other. The first meshed conductive structures and the second meshed conductive structures are alternately stacked.
摘要翻译：电容器结构具有不与第一电极电连接的第一电极和第二电极。第一电极具有多个第一网状导电结构。第一网状导电结构具有相同的布局图案，并且彼此电连接。第二电极具有多个第二网状导电结构。第二网状导电结构具有相同的布局图案，并且彼此电连接。第一网状导电结构和第二网状导电结构交替堆叠。

7. 发明授权

US07199040B2 Barrier layer structure 有权
标题翻译：阻隔层结构
公开(公告)号：US07199040B2
公开(公告)日：2007-04-03
申请号：US10841562
申请日：2004-05-10
申请人： Yu-Ru Yang , Chien-Chung Huang
发明人： Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76844 , H01L21/2855 , H01L21/76846 , H01L21/76862
摘要： A barrier layer structure includes a first dielectric layer forming on a conductive layer and having a via being formed in the first dielectric layer, wherein the via in the first dielectric layer is connected to the conductive layer. A first metal layer is steppedly covered on the first dielectric layer. A layer of metallized materials is steppedly covered on the first metal layer, but the layer of metallized materials does not cover the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. A second metal layer is steppedly covered on the layer of metallized materials, and the second metal layer is covered the first metal layer above the via bottom connected to the conductive layer in the dielectric layer. The barrier layer structure will have lower resistivity in the bottom via of the first dielectric layer and it is capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：阻挡层结构包括在导电层上形成的第一介电层，并且在第一介电层中形成通孔，其中第一介电层中的通孔连接到导电层。第一金属层被阶梯式地覆盖在第一介电层上。金属化材料层被阶梯式地覆盖在第一金属层上，但是金属化材料层不覆盖连接到电介质层中的导电层的通孔底部上的第一金属层。第二金属层被阶梯式地覆盖在金属化材料层上，并且第二金属层覆盖连接到电介质层中的导电层的通孔底部上的第一金属层。阻挡层结构在第一电介质层的底部通孔中具有较低的电阻率，并且能够防止铜原子扩散到电介质层中。

8. 发明申请

US20050250312A1 Structure and process of metal interconnects 有权
公开(公告)号：US20050250312A1
公开(公告)日：2005-11-10
申请号：US11155729
申请日：2005-06-16
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76886 , H01L21/76805 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.

9. 发明授权

US6043148A Method of fabricating contact plug 失效
标题翻译：制造接触塞的方法
公开(公告)号：US6043148A
公开(公告)日：2000-03-28
申请号：US61613
申请日：1998-04-16
申请人： Yuan-Ching Peng , Lih-Juann Chen , Yu-Ru Yang , Win-Yi Hsieh , Yong-Fen Hsieh
发明人： Yuan-Ching Peng , Lih-Juann Chen , Yu-Ru Yang , Win-Yi Hsieh , Yong-Fen Hsieh
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76856 , H01L21/76843
摘要： A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.
摘要翻译：一种制造金属插头的方法。在包括MOS器件，电介质层和穿过电介质层的通孔的半导体衬底上，在电介质层和通孔上形成共形钛层。在氮气环境中形成低温退火，使得钛层的表面转变为第一薄氮化钛层。通过使用准直器溅射在第一薄氮化钛层上形成保形第二氮化钛层。在第二氮化钛层上形成金属层并回蚀刻以形成金属塞。

10. 发明授权

US5990004A Method for forming a tungsten plug and a barrier layer in a contact of high aspect ratio 失效
标题翻译：在高纵横比的接触中形成钨丝塞和阻挡层的方法
公开(公告)号：US5990004A
公开(公告)日：1999-11-23
申请号：US115944
申请日：1998-07-15
申请人： Yu-Ru Yang , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Yu-Ru Yang , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28568 , H01L21/76877
摘要： A method for forming a barrier layer inside a contact in a semiconductor wafer is disclosed herein. The forgoing semiconductor wafer includes a dielectric layer on a silicon contained layer. A portion of the silicon contained layer is exposed by the contact. The method mentioned above includes the following steps.First, form a conductive layer on the topography of the semiconductor wafer by a method other than CVD to increase the ohmic contact to the exposed silicon contained layer. Thus a first portion of the conductive layer is formed on the dielectric layer, and a second portion of the conductive layer is formed on the exposed silicon contained layer. Next, remove the first portion of the conductive layer to expose the dielectric layer. Finally, use a chemical vapor deposition (CVD) method to form the barrier layer on the dielectric layer and the first portion of the conductive layer to prevent said silicon contained layer from exposure.
摘要翻译：本文公开了一种在半导体晶片的接触部内形成阻挡层的方法。前述的半导体晶片包括在含硅层上的电介质层。含硅层的一部分被接触露出。上述方法包括以下步骤。首先，通过CVD以外的方法在半导体晶片的形貌上形成导电层，以增加暴露的含硅层的欧姆接触。因此，导电层的第一部分形成在电介质层上，导电层的第二部分形成在暴露的硅含量层上。接下来，去除导电层的第一部分以暴露电介质层。最后，使用化学气相沉积（CVD）方法在电介质层和导电层的第一部分上形成阻挡层，以防止所述含硅层暴露。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式