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    • 4. 发明授权
    • Apparatus for controlling rotational speed of motor
    • 用于控制电机转速的装置
    • US06810202B2
    • 2004-10-26
    • US10243931
    • 2002-09-16
    • Chia-Chang HsuChung-Hsien Lin
    • Chia-Chang HsuChung-Hsien Lin
    • H02P500
    • H02P6/16Y10S388/915Y10S388/934
    • An apparatus for controlling a rotational speed of a motor, coupled to a sensing unit capable of outputting a sensing signal. The apparatus includes a controlling unit, coupled to the sensing unit, for outputting a controlling signal according to the sensing signal and independently of the rotational speed of the motor. The controlling signal is a square wave and has a duty ratio that is determined by the sensing signal. The apparatus also includes a driving unit, coupled to the controlling unit, for outputting a driving signal to a motor rotor according to the duty ratio of the controlling signal. The driving signal also is a square wave. The rotational speed of the motor rotor is determined by the duty ratio of the driving signal.
    • 一种用于控制电动机的转速的装置,其耦合到能够输出感测信号的感测单元。 该装置包括耦合到感测单元的控制单元,用于根据感测信号输出控制信号,并独立于电动机的转速。 控制信号是方波,具有由感测信号确定的占空比。 该装置还包括驱动单元,其连接到控制单元,用于根据控制信号的占空比将驱动信号输出到电动机转子。 驾驶信号也是方波。 电动机转子的转速由驱动信号的占空比决定。
    • 6. 发明授权
    • Branch prediction and fetch mechanism for variable length instruction,
superscalar pipelined processor
    • 可变长度指令,超标量流水线处理器的分支预测和获取机制
    • US5948100A
    • 1999-09-07
    • US972226
    • 1997-11-17
    • Chia-Chang HsuRuey-Liang MaChien-Kuo TienKun-Cheng Wu
    • Chia-Chang HsuRuey-Liang MaChien-Kuo TienKun-Cheng Wu
    • G06F9/30G06F9/38G06F13/00
    • G06F9/3806G06F9/30149G06F9/3804G06F9/3816G06F9/3844
    • A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.
    • 公开了一种处理器架构,包括一个提取器,分组单元和分支目标缓冲器。 分支目标缓冲器设置有以组合关联方式组织的标签RAM。 响应于接收到搜索地址,标签RAM中的多个集合被同时搜索预测要被采用的分支指令。 分组单元具有包含指令的被存储的高速缓存块所存储的队列。 顺序获取的高速缓存块存储在队列的相邻位置。 队列条目还具有指示指示序列的起始或最终数据字是否包含在队列条目中的指示符,如果是,则指示特定起始数据字或最终数据字的偏移量。 作为响应,分组单元将指令序列的数据字连接成连续的块。 提取器产生一个取出地址,用于从包含要执行的指令的指令高速缓存中提取缓存块。 读取器还生成用于输出到分支目标缓冲区的搜索地址。 响应于分支目标缓冲器检测跨越多个高速缓存块的取得的分支,提取地址增加,使得它指向要获取的下一个高速缓存块,但是搜索地址保持相同。