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1. 发明授权

US5990004A Method for forming a tungsten plug and a barrier layer in a contact of high aspect ratio 失效
标题翻译：在高纵横比的接触中形成钨丝塞和阻挡层的方法
公开(公告)号：US5990004A
公开(公告)日：1999-11-23
申请号：US115944
申请日：1998-07-15
申请人： Yu-Ru Yang , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Yu-Ru Yang , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28568 , H01L21/76877
摘要： A method for forming a barrier layer inside a contact in a semiconductor wafer is disclosed herein. The forgoing semiconductor wafer includes a dielectric layer on a silicon contained layer. A portion of the silicon contained layer is exposed by the contact. The method mentioned above includes the following steps.First, form a conductive layer on the topography of the semiconductor wafer by a method other than CVD to increase the ohmic contact to the exposed silicon contained layer. Thus a first portion of the conductive layer is formed on the dielectric layer, and a second portion of the conductive layer is formed on the exposed silicon contained layer. Next, remove the first portion of the conductive layer to expose the dielectric layer. Finally, use a chemical vapor deposition (CVD) method to form the barrier layer on the dielectric layer and the first portion of the conductive layer to prevent said silicon contained layer from exposure.
摘要翻译：本文公开了一种在半导体晶片的接触部内形成阻挡层的方法。前述的半导体晶片包括在含硅层上的电介质层。含硅层的一部分被接触露出。上述方法包括以下步骤。首先，通过CVD以外的方法在半导体晶片的形貌上形成导电层，以增加暴露的含硅层的欧姆接触。因此，导电层的第一部分形成在电介质层上，导电层的第二部分形成在暴露的硅含量层上。接下来，去除导电层的第一部分以暴露电介质层。最后，使用化学气相沉积（CVD）方法在电介质层和导电层的第一部分上形成阻挡层，以防止所述含硅层暴露。

2. 发明授权

US6146742A Barrier/glue layer on polysilicon layer 失效
标题翻译：多晶硅层上的阻挡层/胶层
公开(公告)号：US6146742A
公开(公告)日：2000-11-14
申请号：US34793
申请日：1998-03-03
申请人： Wen-Yi Hsieh , Chi-Rong Lin , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Wen-Yi Hsieh , Chi-Rong Lin , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/28 , H01L29/49 , H01L23/48
CPC分类号： H01L29/4941 , H01L21/28061 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926 , Y10T428/31678
摘要： A method for forming a barrier/glue layer above the polysilicon layer of a MOS transistor gate comprising the step of providing a semiconductor substrate, and then forming a gate oxide layer above the substrate. Next, a polysilicon layer is formed over the gate oxide layer. Thereafter, a titanium layer is deposited over the polysilicon layer first, and then a titanium nitride layer is deposited above the titanium layer. This titanium/titanium nitride bi-layer is capable of increasing the adhesive strength with a subsequently deposited tungsten silicide layer, and preventing the peeling of the tungsten silicide layer. Furthermore, the titanium nitride layer acts as a barrier for fluorine atoms preventing their diffusion to the gate oxide layer/polysilicon layer interface, and affecting the effective thickness of the gate oxide layer. In the subsequent step, a tungsten suicide layer is formed above the titanium nitride layer. Finally, after an annealing operation, the titanium layer will react with the silicon in the polysilicon layer and the tungsten silicide layer to form a titanium silicide layer. Hence, the resistance of the polycide layer in a MOS transistor gate can be reduced.
摘要翻译：一种用于在MOS晶体管栅极的多晶硅层上形成阻挡/胶合层的方法，包括提供半导体衬底，然后在衬底上形成栅氧化层的步骤。接下来，在栅极氧化物层上形成多晶硅层。此后，首先在多晶硅层上沉积钛层，然后在钛层上方沉积氮化钛层。该钛/氮化钛双层能够随后沉积的硅化钨层增加粘合强度，并且防止硅化钨层的剥离。此外，氮化钛层用作氟原子的阻挡层，防止其扩散到栅极氧化物层/多晶硅层界面，并影响栅极氧化物层的有效厚度。在随后的步骤中，在氮化钛层的上方形成硅化钨层。最后，在退火操作之后，钛层将与多晶硅层中的硅和硅化钨层反应形成硅化钛层。因此，可以降低MOS晶体管栅极中的多晶硅化物层的电阻。

3. 发明授权

US6030892A Method of preventing overpolishing in a chemical-mechanical polishing operation 失效
标题翻译：在化学机械抛光操作中防止过度抛光的方法
公开(公告)号：US6030892A
公开(公告)日：2000-02-29
申请号：US866131
申请日：1997-05-30
申请人： Kun-Lin Wu , Hao-Kuang Chiu , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Kun-Lin Wu , Hao-Kuang Chiu , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/3105 , H01L21/4763
CPC分类号： H01L21/31053
摘要： A method of preventing overpolishing in a chemical-mechanical polishing operation includes using a spin-on polymer material instead of spin-on glass as the local planarization material. The spin-on polymer layer is further used as a polishing stop layer so as to prevent damage to components due to overpolishing, because the polishing rate of the spin-on polymer layer in a chemical-mechanical polishing operation is, in general, lower than the polishing rate of the silicon dioxide layer formed using plasma enhanced chemical vapor deposition.
摘要翻译：在化学机械抛光操作中防止过度抛光的方法包括使用旋涂聚合物材料代替旋涂玻璃作为局部平坦化材料。旋涂聚合物层进一步用作抛光停止层，以防止由于过度抛光而损坏组分，因为化学机械抛光操作中的旋涂聚合物层的抛光速率通常低于使用等离子体增强化学气相沉积形成的二氧化硅层的抛光速率。

4. 发明授权

US5883014A Method for treating via sidewalls with hydrogen plasma 失效
标题翻译：用氢等离子体处理通孔侧壁的方法
公开(公告)号：US5883014A
公开(公告)日：1999-03-16
申请号：US968746
申请日：1997-08-05
申请人： Shiaw-Rong Chen , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Shiaw-Rong Chen , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/30 , H01L21/316 , H01L21/768 , H01L21/02
CPC分类号： H01L21/76831 , H01L21/3003 , H01L21/316 , H01L21/76826
摘要： A method for treating via sidewalls comprising the steps of providing a substrate having a number of metallic wires already formed; depositing a liner oxide layer; depositing an organic spin-on-glass layer; and depositing a second oxide layer. The second oxide layer is planarized by a chemical-mechanical polishing method. Photolithographic and etching methods, employing oxygen plasma treatment as well as a wet etching removal method are used to form vias above the metallic layers. A hydrogen plasma treatment is performed for the via sidewalls to prevent the occurrence of out-gassing and to obtain superior electrical properties. A titanium/titanium nitride film is deposited, and aluminium or tungsten is deposited into the vias and to form aluminium or tungsten plugs, thus completing the manufacturing process according to this invention. A semiconductor device formned by this method is also described.
摘要翻译：一种用于处理通孔侧壁的方法，包括以下步骤：提供具有已经形成的多个金属线的基底; 沉积衬里氧化物层; 沉积有机旋涂玻璃层; 和沉积第二氧化物层。通过化学机械抛光方法对第二氧化物层进行平面化。使用氧等离子体处理的光刻和蚀刻方法以及湿蚀刻去除方法来在金属层上方形成通孔。对通孔侧壁进行氢等离子体处理，以防止排气的发生并获得优异的电气性能。沉积钛/氮化钛膜，并将铝或钨沉积到通孔中并形成铝或钨插塞，从而完成根据本发明的制造过程。还描述了通过该方法形成的半导体器件。

5. 发明授权

US5876508A Method of cleaning slurry remnants after the completion of a chemical-mechanical polish process 失效
标题翻译：在化学机械抛光工艺完成后清洗浆料残留物的方法
公开(公告)号：US5876508A
公开(公告)日：1999-03-02
申请号：US818898
申请日：1997-03-17
申请人： Kun-Lin Wu , Chien-Hsien Lai , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Kun-Lin Wu , Chien-Hsien Lai , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： B08B3/02 , B24B37/04 , B24B53/007 , C11D3/39 , C11D7/06 , C11D7/08 , H01L21/306 , C03C25/00 , C23G1/02
CPC分类号： H01L21/02052 , B08B3/02 , B24B37/04 , B24B53/017 , C11D3/3947 , C11D7/06 , C11D7/08 , H01L21/30625 , Y10S438/959
摘要： A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature. This can allow an increase in the repellent force between the particles of the slurry remnants and the underlying polishing pad that is caused by the so-called zeta potential, thus allowing the slurry remnants to be more easily removed from the polishing pad.
摘要翻译：提供了在完成化学机械抛光（CMP）工艺之后有效地清洁留在抛光垫上的浆料残余物的方法。该方法能够基本上彻底地清除留在抛光垫上的所有浆料残余物。在本发明的方法中，第一步是制备一种清洗剂，它是以预定比例混合的H 2 O 2，去离子水，酸性溶液和碱性溶液的混合物。随后将清洁剂引导到形成在修整器中的喷嘴。这样可以将洗涤剂强制地喷射到抛光垫上的浆料残余物上，以清除离开抛光垫的浆料残余物。可以为各种浆料提供预定比例的清洗剂，使清洗剂本质上可以调节为酸性或碱性。这可以增加由所谓的ζ电位引起的浆料残留物的颗粒和下面的抛光垫之间的驱除力，从而使浆料残余物更容易从抛光垫上去除。

6. 发明授权

US6093639A Process for making contact plug 失效
标题翻译：接触插头的工艺
公开(公告)号：US6093639A
公开(公告)日：2000-07-25
申请号：US739853
申请日：1996-10-30
申请人： Clint Wu , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Clint Wu , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76864 , H01L21/76843
摘要： A process for fabricating contact plugs for semiconductor IC devices. An insulating layer is formed over the surface of an IC substrate. The insulating layer is then patterned for forming contact vias revealing the surface of an electrically conductive region of the IC circuitry that requires electrical connections by the contact plugs. A glue (adhesive) layer is then formed over the sidewall surface inside the contact vias. The glue (adhesive) layer is densified by either a rapid thermal annealing or a plasma treatment in order to prevent the formation of voids when the plugs are formed. The internal space of the contact vias are then filled with an electrically conductive material to form the contact plugs. The surface of the device substrate is then polished to remove the electrically conductive material and glue layer covering the surface of the insulating layer until the insulating layer surface is exposed, and top surface of the formed contact plug is planarized flat with the surface of the insulating layer.
摘要翻译：一种用于制造用于半导体IC器件的接触插塞的工艺。在IC基板的表面上形成绝缘层。然后对绝缘层进行图案化，以形成接触通孔，该接触通孔显示IC电路的导电区域的表面，该导电区域需要通过接触插头进行电连接。然后在接触通孔内部的侧壁表面上形成胶（粘合剂）层。胶粘剂（粘合剂）层通过快速热退火或等离子体处理来致密化，以防止在形成插塞时形成空隙。然后用导电材料填充接触孔的内部空间以形成接触塞。然后抛光器件衬底的表面以去除覆盖绝缘层的表面的导电材料和胶层，直到绝缘层表面露出，并且形成的接触插塞的顶表面与绝缘体的表面平坦化层。

7. 发明授权

US5950108A Method of fabricating a conductive plug 失效
标题翻译：制造导电插头的方法
公开(公告)号：US5950108A
公开(公告)日：1999-09-07
申请号：US768855
申请日：1996-12-17
申请人： Clint Wu , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Clint Wu , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76862 , H01L21/76843 , H01L21/76877
摘要： A method of forming a conductive plug is disclosed. A device with a conductive region is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. The insulating layer is etched to form a contact window which exposes the conductive region of the device. A diffusion barrier layer is formed on the exposed conductive region and the periphery of the contact window. A hydrogen plasma treatment is performed in a reaction chamber; and a conductive material is filled in the contact window, to form the conductive plug.
摘要翻译：公开了一种形成导电插塞的方法。具有导电区域的器件形成在半导体衬底上。绝缘层形成在半导体衬底上。绝缘层被蚀刻以形成暴露该器件的导电区域的接触窗口。在暴露的导电区域和接触窗的周边上形成扩散阻挡层。在反应室中进行氢等离子体处理; 并且导电材料填充在接触窗口中，以形成导电插塞。

8. 发明授权

US5883004A Method of planarization using interlayer dielectric 失效
标题翻译：使用层间电介质的平面化方法
公开(公告)号：US5883004A
公开(公告)日：1999-03-16
申请号：US920172
申请日：1997-08-25
申请人： Hao-Kuang Shiu , Kun-Lin Wu , Horng-Bor Lu , Jenn-Tarng Lin
发明人： Hao-Kuang Shiu , Kun-Lin Wu , Horng-Bor Lu , Jenn-Tarng Lin
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76819
摘要： A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.
摘要翻译：公开了一种平面化层间电介质的方法。本发明包括首先在半导体衬底上形成阻挡层。接下来，通过旋涂玻璃技术在阻挡层上形成缓冲层。在缓冲层上形成电介质层，其中介电层的蚀刻速率大于缓冲层的蚀刻速率，势垒层用作来自电介质层的自掺杂块。最后，使用缓冲层作为缓冲层来回蚀介电层，从而平坦化介电层。

9. 发明授权

US06136164A Apparatus for detecting position of collimator in sputtering processing chamber 失效
标题翻译：用于检测溅射处理室中准直器位置的装置
公开(公告)号：US06136164A
公开(公告)日：2000-10-24
申请号：US115743
申请日：1998-07-15
申请人： Ing-Tang Chen , Horng-Bor Lu
发明人： Ing-Tang Chen , Horng-Bor Lu
IPC分类号： C23C14/34 , C23C14/54 , H01J37/34
CPC分类号： H01J37/3447 , C23C14/34 , C23C14/54 , H01J37/34
摘要： An apparatus for detecting the position of a collimator in a sputter-processing chamber is disclosed in the present invention. A target holder is at the upper portion of the chamber and a target is attached to the bottom surface of the target holder. A substrate holder is at the underlying portion of the chamber and it is opposed to the target holder. A silicon wafer is putted on the substrate holder. Two supporters are on an inner surface of the housing of the chamber and are separated to oppose to each other, the supporters protrude the housing. A collimator is putted on the supporters and it is parallel to the surface of the target. Two sensors is attached on the under surface or the lateral surface of the supporters. The horizontal height of the sensors is lower than that of the collimator. When the collimator is heated and it distorts, the position of the collimator will change to enter into the available area of the sensors. Afterwards, an alarm will announce a notice to supervisors of the sputtering system.
摘要翻译：在本发明中公开了一种用于在溅射处理室中检测准直器的位置的装置。目标支架位于腔室的上部，目标支架安装在目标支架的底面上。衬底保持器位于腔室的下部，并且与靶保持器相对。将硅晶片放置在基板保持器上。两个支持者位于房间的壳体的内表面上并被分离以相互对置，支撑者突出壳体。准直器放在支架上，平行于目标表面。两个传感器连接在支撑者的下表面或侧面上。传感器的水平高度低于准直仪。当准直器被加热并且其变形时，准直器的位置将改变以进入传感器的可用区域。之后，一个报警器将通知一个溅射系统的主管。

10. 发明授权

US06013559A Method of forming trench isolation 有权
标题翻译：形成沟槽隔离的方法
公开(公告)号：US06013559A
公开(公告)日：2000-01-11
申请号：US172465
申请日：1998-10-14
申请人： Kun-Lin Wu , Horng-Bor Lu
发明人： Kun-Lin Wu , Horng-Bor Lu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method of fabricating a trench isolation structure in a semiconductor devices. First, a mask layer is formed on a substrate and patterned. Then, a trench is formed in the substrate using the mask layer as a mask. An insulating layer is formed under the mask layer to fill the trench. The insulating layer is polished to expose a portion of the mask layer and an insulating plug is left in the trench. A RTP is performed to avoid mobile ions diffuse into the substrate. There are several operating conditions for the RTP. For example the operating temperature is ranged from about 600.degree. C. to about 1300.degree. C. The duration for performing the RTP is ranged from about 5 seconds to about 5 minutes. The operating gas can be selected from one of a group of N.sub.2, O.sub.2, or N.sub.2 O. Besides, before the RTP a cleaning step is performed using SC-1 or hydrogen fluoride (HF) solution as cleaning solution.
摘要翻译：一种在半导体器件中制造沟槽隔离结构的方法。首先，在基板上形成掩模层并进行图案化。然后，使用掩模层作为掩模在衬底中形成沟槽。在掩模层之下形成绝缘层以填充沟槽。抛光绝缘层以露出掩模层的一部分，并且绝缘插头留在沟槽中。执行RTP以避免移动离子扩散到衬底中。 RTP有几种操作条件。例如，操作温度范围为约600℃至约1300℃。执行RTP的持续时间为约5秒至约5分钟。工作气体可以选自一组N2，O2或N2O中的一种。此外，在RTP之前，使用SC-1或氟化氢（HF）溶液作为清洁溶液进行清洁步骤。

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