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    • 4. 发明授权
    • Method for fabricating a multistage phase shift mask
    • 制造多级相移掩模的方法
    • US5882534A
    • 1999-03-16
    • US443398
    • 1995-05-17
    • Young Jin Song
    • Young Jin Song
    • G03F1/28G03F1/30H01L21/027G03F1/00
    • G03F1/28G03F1/30
    • A multistage phase shift mask includes a light transmissive substrate having light shielding regions and light transmissive regions. A shielding layer is disposed on the shielding regions of the substrate and a phase shifter layer extends over the light transmissive regions between a pair of the shielding regions. A first etched portion on the substrate is adjacent to the phase shifter layer that contacts with the substrate and a second etched portion on the substrate is between the phase shifter layer and the first etched portion of the substrate.The second etched portion consists of a gradual concave slope allowing a phase shift from approximately 0 to 180 degrees.
    • 多级相移掩模包括具有遮光区域和透光区域的透光基板。 屏蔽层设置在衬底的屏蔽区域上,并且移相器层在一对屏蔽区域之间的透光区域上延伸。 衬底上的第一蚀刻部分与与衬底接触的移相器层相邻,衬底上的第二蚀刻部分位于衬底的移相器层和第一蚀刻部分之间。 第二蚀刻部分由允许相位从大约0到180度的渐变凹斜面组成。
    • 5. 发明授权
    • Transistor fabrication method
    • 晶体管制造方法
    • US5869375A
    • 1999-02-09
    • US796038
    • 1997-02-05
    • Jong-Moon ChoiYoung Jin SongChang Reol Kim
    • Jong-Moon ChoiYoung Jin SongChang Reol Kim
    • H01L29/78H01L21/336H01L29/423H01L29/739
    • H01L29/78H01L29/66628
    • A method for fabricating a transistor includes the steps of forming a gate insulation film on a substrate, forming a gate electrode on the gate insulation film and forming a first insulation film pattern on the gate electrode. A side wall spacer is formed at side surfaces of the first insulation film pattern and the gate electrode. The gate insulation film is etched to expose a portion of a surface of the substrate. An epitaxial layer is formed on the substrate where the gate insulation film is etched. The side wall spacer is removed and a thermal oxide film is grown on a portion corresponding to where the side wall spacer is removed and on an upper portion of the epitaxial layer. A source/drain region is formed by ion-implanting an impurity into the epitaxial layer.
    • 一种制造晶体管的方法包括以下步骤:在衬底上形成栅极绝缘膜,在栅极绝缘膜上形成栅电极,并在栅电极上形成第一绝缘膜图案。 在第一绝缘膜图案和栅电极的侧表面处形成侧壁间隔物。 蚀刻栅极绝缘膜以暴露基板表面的一部分。 在栅极绝缘膜被蚀刻的基板上形成外延层。 除去侧壁间隔物,并且在与去除侧壁间隔物的部分相对应的部分上和在外延层的上部上生长热氧化膜。 通过将杂质离子注入到外延层中形成源/漏区。
    • 6. 发明授权
    • Method for forming multi-layer resist pattern
    • 形成多层抗蚀剂图案的方法
    • US5700626A
    • 1997-12-23
    • US673476
    • 1996-07-01
    • Jun Seok LeeHun HurYoung Jin Song
    • Jun Seok LeeHun HurYoung Jin Song
    • G03F7/26G03F7/00G03F7/09H01L21/027H01L21/30
    • G03F7/094G03F7/0035Y10S430/143Y10S438/949Y10S438/95
    • A method for forming a multi-layer resist (MLR) pattern capable of preventing a generation of a charge-up effect in an exposure to electron beams and reducing alignment detect errors, and employing a silylation process, thereby achieving an improvement in resonance. The method includes the steps of forming a primary alignment mark on a silicon substrate formed with a cell part including a plurality of cell patterns having steps, depositing a lower deposition film over the silicon substrate, coating a lower resist film over the lower deposition film, subjecting a portion of the lower resist film to a light exposure and a development to form a secondary alignment mark, forming an intermediate insulating layer over the lower resist film, coating an upper resist film over the intermediate insulating layer to form a MLR film, subjecting the upper resist film to a light exposure to fork a latent image pattern at a non-exposed portion of the upper resist film, subjecting the resulting structure to a silylation to form a silylated layer over the upper resist film, etching the upper resist film to form an upper resist pattern and removing the silylated layer, patterning the intermediate insulating layer by use of the upper resist pattern as a mask, and etching the lower resist film by use of the intermediate insulating layer as a mask, thereby forming a MLR pattern.
    • 一种用于形成能够防止在电子束曝光中产生电荷效应并降低取向检测误差的多层抗蚀剂(MLR)图案的方法,并且采用甲硅烷化处理,从而实现共振的改善。 该方法包括以下步骤:在形成有包括多个单元图案的单元部分的硅衬底上形成主对准标记,该步骤包括在硅衬底上沉积下沉积膜,在下沉积膜上涂覆下抗蚀膜, 使下部抗蚀剂膜的一部分曝光和显影以形成二次对准标记,在下部抗蚀剂膜上形成中间绝缘层,在中间绝缘层上涂覆上部抗蚀剂膜以形成MLR膜, 上抗蚀剂膜曝光以在上抗蚀剂膜的未曝光部分处分散潜像图案,使所得结构进行甲硅烷基化以在上抗蚀剂膜上形成甲硅烷基化层,将上抗蚀剂膜蚀刻至 形成上抗蚀剂图案并除去甲硅烷基化层,通过使用上抗蚀剂图案作为掩模等将中间绝缘层图案化等 通过使用中间绝缘层作为掩模来将下抗蚀剂膜铰接,由此形成MLR图案。
    • 9. 发明授权
    • Process for making a semiconductor MOS transistor
    • 制造半导体MOS晶体管的工艺
    • US5604138A
    • 1997-02-18
    • US357961
    • 1994-12-15
    • Chang-Jae LeeYoung-Jin Song
    • Chang-Jae LeeYoung-Jin Song
    • H01L21/28H01L21/336H01L21/469H01L29/78H01L21/8234
    • H01L29/6659H01L21/28123
    • A process for forming an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer on the second insulating layer; forming an etch inhibiting layer pattern for forming an over-sized gate on a relevant area of the second insulating layer; removing the second and third insulating layers and the conductive layer excluding the portions protected from the etch inhibiting layer, so as to form a stacked pattern consisting of the residual second insulating layer/the third insulating layer/the conductive layer; forming a first impurity ion buried layer on a relevant portion of the semiconductor substrate utilizing the stacked pattern for formation of a source/drain region; removing the etch inhibiting layer; removing an edge portion of the remaining second insulating layer of the stacked pattern for forming the final gate; removing the residual third insulating layer of the stacked pattern; etching the residual conductive layer by using the partly removed second insulating layer as the mask to form the final gate; forming a second impurity ion buried layer on the relevant portion of the semiconductor substrate for forming the LDD structure; forming a fourth insulating layer on the whole surface of the wafer; and activating the first and second ion buried layers.
    • 公开了一种用于形成具有LDD结构的MOS半导体器件的工艺,其可以包括以下步骤:在半导体衬底上形成第一绝缘层; 在所述第一绝缘层上形成导电层; 在所述导电层上形成第二绝缘层; 在所述第二绝缘层上形成第三绝缘层; 形成用于在所述第二绝缘层的相关区域上形成超大尺寸栅极的蚀刻抑制层图案; 除去不受蚀刻抑制层保护的部分的第二绝缘层和第三绝缘层和导电层,以形成由残留的第二绝缘层/第三绝缘层/导电层组成的层叠图案; 使用用于形成源极/漏极区域的堆叠图案在半导体衬底的相关部分上形成第一杂质离子掩埋层; 去除蚀刻抑制层; 去除用于形成最终栅极的层叠图案的剩余第二绝缘层的边缘部分; 去除堆叠图案的残余第三绝缘层; 通过使用部分去除的第二绝缘层作为掩模来蚀刻残留导电层以形成最终栅极; 在所述半导体衬底的相关部分上形成第二杂质离子掩埋层以形成所述LDD结构; 在晶片的整个表面上形成第四绝缘层; 并激活第一和第二离子掩埋层。
    • 10. 发明授权
    • Multiple wavelength surface-emitting laser device and method for its manufacture
    • 多波长表面发射激光器件及其制造方法
    • US06795457B2
    • 2004-09-21
    • US09867709
    • 2001-05-31
    • Young-jin SongSeung-ho NamByoung-lyong ChoiJae-ho You
    • Young-jin SongSeung-ho NamByoung-lyong ChoiJae-ho You
    • H01S310
    • H01S5/423H01S5/0425H01S5/18311H01S5/18361H01S5/4087
    • A multiple wavelength surface-emitting laser device equipped with a substrate and a plurality of surface-emitting lasers formed on the substrate by a continuous manufacturing process is provided. Each surface-emitting laser includes a bottom reflection layer on the substrate, that is doped with impurities of one type and composed of alternating semiconductor material layers having different refractive indexes; an active layer that is formed on the bottom reflection layer; an intermediate layer that is doped with impurities of the other type on the active layer; a top electrode that is formed on the intermediate layer to have a window through which light is emitted; and a dielectric reflection layer where dielectric materials with different refractive indexes are alternately layered on the intermediate layer and/or the top electrode to a thickness suitable for a desired resonance wavelength, and the resonance wavelength is controlled by adjusting the thickness of the dielectric reflection layer.
    • 提供了通过连续制造工艺配置有基板和形成在基板上的多个表面发射激光器的多波长表面发射激光器件。 每个表面发射激光器包括在衬底上的底部反射层,其掺杂了一种类型的杂质,并且由具有不同折射率的交替的半导体材料层组成; 形成在底部反射层上的有源层; 在活性层上掺杂另一种杂质的中间层; 形成在所述中间层上以具有通过其发出光的窗口的顶部电极; 以及介电反射层,其中具有不同折射率的电介质材料在中间层和/或顶部电极上交替层叠到适于所需共振波长的厚度,并且通过调节介电反射层的厚度来控制谐振波长 。