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    • 4. 发明授权
    • Method of forming semiconductor integrated device
    • 形成半导体集成器件的方法
    • US07208359B2
    • 2007-04-24
    • US11134386
    • 2005-05-23
    • Naohiro UedaYoshinori Ueda
    • Naohiro UedaYoshinori Ueda
    • H01L21/8234
    • H01L21/823857H01L21/823892H01L27/0922H01L27/0928
    • A semiconductor device is provided comprising several device components formed in the same substrate, such as a P-substrate having an offset Nch transistor including N-type source and drain each formed in a P-well spatially separated from one another, and the drain surrounded by a low concentration N-type diffusion layer; an offset Pch transistor including P-type source and drain each formed in an N-well spatially separated from one another, and the drain surrounded by a low concentration P-type diffusion layer; a triple well including a deep N-well, and a P-type IP well formed therein; a normal N-well for forming a Pch MOS transistor; and a normal P-well for forming an Nch MOS transistor; in which simultaneously formed are the low concentration N-type diffusion layer, N-well and normal N-well; the P-well and normal P-well; and the low concentration P-type diffusion layer and IP well.
    • 提供了一种半导体器件,其包括形成在同一衬底中的若干器件组件,例如具有偏置N沟道晶体管的P衬底,其中N型晶体管包括N型源极和漏极,其各自形成在彼此空间上分离的P阱中,并且漏极包围 通过低浓度N型扩散层; 偏移Pch晶体管,包括P型源极和漏极,各自形成在空间上彼此分离的N阱中,并且由低浓度P型扩散层包围的漏极; 包括深N阱的三阱和在其中形成的P型IP阱; 用于形成Pch MOS晶体管的正常N阱; 以及用于形成Nch MOS晶体管的正常P阱; 其中同时形成低浓度N型扩散层,N阱和正常N阱; P井和正常P井; 和低浓度P型扩散层和IP井。
    • 7. 发明授权
    • Voltage reference generation circuit and power source incorporating such circuit
    • 电压基准信号生成电路和并入电路的电源
    • US06798278B2
    • 2004-09-28
    • US10376277
    • 2003-03-03
    • Yoshinori Ueda
    • Yoshinori Ueda
    • G05F324
    • G05F3/24
    • A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference. In addition, each of the enhancement-mode MOS transistors is provided with a floating gate having a different threshold voltage depending on, the coupling coefficient between the floating gate and a gate, the amount of charge input to the floating gate, the kind of dielectric material included in the gate, or the thickness of a gate oxide layer, which is suitably utilized to supply reference voltages with improved stability to fluctuations in operating temperatures or processing parameters.
    • 公开了一种参考电压生成电路,其包括:耗能型MOS晶体管和增强型MOS晶体管串联连接的电压基准产生级和电压基准输出级,并且在这些MOS晶体管之间形成的结为 输出端子,用于输出要输入到电压参考输出级的电压。 在输出级中,具有相同沟道掺杂分布的两个增强型MOS晶体管串联连接在电源和地之间,一个MOS晶体管的栅极连接到发生级的输出端,栅极和漏极 并且这些MOS晶体管之间形成的结用作用于电压基准的输出端子。 此外,增强型MOS晶体管中的每一个都具有取决于浮置栅极和栅极之间的耦合系数,输入到浮动栅极的电荷量,电介质的种类,具有不同阈值电压的浮置栅极 包括在栅极中的材料或栅极氧化物层的厚度,其适合用于为工作温度或处理参数的波动提供改进的稳定性的参考电压。