专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100144090A1 PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有双下电极的相变存储器件及其制造方法
公开(公告)号：US20100144090A1
公开(公告)日：2010-06-10
申请号：US12709536
申请日：2010-02-22
申请人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
发明人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
IPC分类号： H01L21/02
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

2. 发明授权

US08129214B2 Phase change memory devices having dual lower electrodes and methods of fabricating the same 有权
标题翻译：具有双下电极的相变存储器件及其制造方法
公开(公告)号：US08129214B2
公开(公告)日：2012-03-06
申请号：US12709536
申请日：2010-02-22
申请人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
发明人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
IPC分类号： H01L21/00 , H01L45/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

3. 发明授权

US07696508B2 Phase change memory devices having dual lower electrodes 有权
标题翻译：具有双下电极的相变存储器件
公开(公告)号：US07696508B2
公开(公告)日：2010-04-13
申请号：US11932781
申请日：2007-10-31
申请人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
发明人： Yoon-Jong Song , Kyung-Chang Ryoo , Dong-Won Lim
IPC分类号： H01L29/43
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/1675
摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。包括通过下层间绝缘层并露出衬底的开口。掩埋绝缘图案设置在开口中。依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。还提供了制造半导体器件的方法。

4. 发明申请

US20090230376A1 RESISTIVE MEMORY DEVICES 有权
标题翻译：电阻式存储器件
公开(公告)号：US20090230376A1
公开(公告)日：2009-09-17
申请号：US12273140
申请日：2008-11-18
申请人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
发明人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
IPC分类号： H01L47/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line
摘要翻译：提供了可以以高集成度密度集成的电阻式存储器件及其形成方法。在一个实施例中，使用大马士革技术由铜形成位线，并且当铜位线可以在铜位线周围形成铜螺柱

5. 发明授权

US08384060B2 Resistive memory device 有权
标题翻译：电阻式存储器件
公开(公告)号：US08384060B2
公开(公告)日：2013-02-26
申请号：US12273140
申请日：2008-11-18
申请人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
发明人： Kyung-Chang Ryoo , Jae-Hee Oh , Jung-Hoon Park , Hyeong-Jun Kim , Dong-Won Lim
IPC分类号： H01L47/00 , H01L29/06 , H01L21/02 , H01L21/336 , G11C11/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line.
摘要翻译：提供了可以以高集成度密度集成的电阻式存储器件及其形成方法。在一个实施例中，使用大马士革技术由铜形成位线，并且当铜位线可以围绕铜位线形成铜螺柱时。

6. 发明申请

US20090230378A1 RESISTIVE MEMORY DEVICES 审中-公开
标题翻译：电阻式存储器件
公开(公告)号：US20090230378A1
公开(公告)日：2009-09-17
申请号：US12273271
申请日：2008-11-18
申请人： Kyung-Chang Ryoo , Hong-Sik Jeong , Gi-Tae Jeong , Hyeong-Jun Kim , Dong-Won Lim
发明人： Kyung-Chang Ryoo , Hong-Sik Jeong , Gi-Tae Jeong , Hyeong-Jun Kim , Dong-Won Lim
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1683
摘要： Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. An insulating layer enclosing a resistive memory element and an insulating layer enclosing a conductive line connected with the resistive memory element have different stresses, hardness, porosity degrees, dielectric constant or heat conductivities.
摘要翻译：提供了可以以高集成度密度集成的电阻式存储器件及其形成方法。包围电阻性存储元件的绝缘层和包围与电阻式存储元件连接的导线的绝缘层具有不同的应力，硬度，孔隙度，介电常数或导热系数。

7. 发明申请

US20090242866A1 Phase change memory device and method of fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090242866A1
公开(公告)日：2009-10-01
申请号：US12382781
申请日：2009-03-24
申请人： Seung-Pil Ko , Jae-Hee Oh , Jung-Hoon Park , Yoon-Jong Song , Jae-Hyun Park , Dong-Won Lim
发明人： Seung-Pil Ko , Jae-Hee Oh , Jung-Hoon Park , Yoon-Jong Song , Jae-Hyun Park , Dong-Won Lim
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.
摘要翻译：半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。

8. 发明申请

US20090026436A1 Phase change memory devices and methods of forming the same 失效
标题翻译：相变存储器件及其形成方法
公开(公告)号：US20090026436A1
公开(公告)日：2009-01-29
申请号：US12219647
申请日：2008-07-25
申请人： Yoon-Jong Song , Seung-Pil Ko , Dong-Won Lim
发明人： Yoon-Jong Song , Seung-Pil Ko , Dong-Won Lim
IPC分类号： H01L47/00 , H01L21/28
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/16
摘要： A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode.
摘要翻译：形成相变存储器件的方法包括在衬底上形成芯图案，在包括芯图案的衬底上共形形成导热层，各向异性地将导热层刻蚀成芯图案的顶表面，以形成围绕芯图案的侧壁的热电极，以及形成连接到热电极的顶表面的相变存储器图案。

9. 发明授权

US07939366B2 Phase change memory devices and methods of forming the same 失效
标题翻译：相变存储器件及其形成方法
公开(公告)号：US07939366B2
公开(公告)日：2011-05-10
申请号：US12219647
申请日：2008-07-25
申请人： Yoon-Jong Song , Seung-Pil Ko , Dong-Won Lim
发明人： Yoon-Jong Song , Seung-Pil Ko , Dong-Won Lim
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/16
摘要： A method of forming a phase change memory device includes forming a core pattern on a substrate, conformally forming a heat conductive layer on the substrate including the core pattern, anisotropically etching the heat conductive layer down to a top surface of the core pattern to form a heat electrode surrounding a sidewall of the core pattern, and forming a phase change memory pattern connected to a top surface of the heat electrode.
摘要翻译：形成相变存储器件的方法包括在衬底上形成芯图案，在包括芯图案的衬底上共形形成导热层，各向异性地将导热层刻蚀成芯图案的顶表面，以形成围绕芯图案的侧壁的热电极，以及形成连接到热电极的顶表面的相变存储器图案。

10. 发明授权

US07906773B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07906773B2
公开(公告)日：2011-03-15
申请号：US12382781
申请日：2009-03-24
申请人： Seung-Pil Ko , Jae-Hee Oh , Jung-Hoon Park , Yoon-Jong Song , Jae-Hyun Park , Dong-Won Lim
发明人： Seung-Pil Ko , Jae-Hee Oh , Jung-Hoon Park , Yoon-Jong Song , Jae-Hyun Park , Dong-Won Lim
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1683
摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.
摘要翻译：半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式