专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06122698A Data bus having conducting lines driven at multiple adjustable current levels to transfer multiple-bit data on each conducting line 失效
标题翻译：数据总线具有以多个可调电流电平驱动的导线，以在每条导线上传输多位数据
公开(公告)号：US06122698A
公开(公告)日：2000-09-19
申请号：US61631
申请日：1998-04-16
申请人： Yong Sik Seok
发明人： Yong Sik Seok
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4072 , Y02B60/1228 , Y02B60/1235
摘要： A bus interface system and method includes a driver circuit and a receiver circuit coupled on opposite ends of a conducting line of a bus. The driver circuit drives an adjustable current through the conducting line to the receiver circuit. The current level of the adjustable current can be adjusted to one of several levels according to the data item being transferred across the line. The receiver circuit receives the adjustable current and detects the level of the current to identify the information encoded by the signal being transferred. The current level can be set to one of several values such that the information being transferred by the signal can be in one of several possible states. The system therefore is capable of encoding more data than binary systems. Higher data bus transfer rates can therefore be realized.
摘要翻译：总线接口系统和方法包括驱动电路和耦合在总线的导线的相对端上的接收器电路。驱动电路通过导线将可调电流驱动到接收器电路。可调节电流的当前电平可以根据跨线路传输的数据项目调整为多个电平之一。接收器电路接收可调电流并检测电流的电平以识别被传送信号编码的信息。可以将当前电平设置为几个值之一，使得由信号传送的信息可以处于几种可能状态之一。因此，该系统能够比二进制系统编码更多的数据。因此可以实现更高的数据总线传输速率。

2. 发明授权

US5396465A Circuit for controlling isolation transistors in a semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中的隔离晶体管的电路
公开(公告)号：US5396465A
公开(公告)日：1995-03-07
申请号：US156779
申请日：1993-11-24
申请人： Seung-Cheol Oh , Yong-Sik Seok
发明人： Seung-Cheol Oh , Yong-Sik Seok
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C7/1006 , G11C29/50 , G11C11/401
摘要： A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.
摘要翻译：半导体存储器件具有设置在公共位读出放大器和存储器阵列之间的相邻存储器阵列和隔离晶体管。根据本发明的隔离控制电路在老化操作模式期间产生电源电压Vcc（而不是升压电压Vpp），从而防止隔离晶体管的栅极氧化层被破坏或劣化。

3. 发明授权

US5991903A Parallel bit test circuit for testing a semiconductor device in parallel bits 失效
标题翻译：并行位测试电路，用于并行位测试半导体器件
公开(公告)号：US5991903A
公开(公告)日：1999-11-23
申请号：US909300
申请日：1997-08-11
申请人： Choong-Sun Shin , Yong-Sik Seok
发明人： Choong-Sun Shin , Yong-Sik Seok
IPC分类号： G01R31/28 , G11C29/26 , G11C29/34 , G11C29/38 , H01L21/66 , G11C29/00 , G06F7/02
CPC分类号： G11C29/26 , G11C29/38
摘要： A novel parallel bit test circuit is provided to test a semiconductor memory device which comprises a number of memory cell arrays each having a plurality of memory cells, a word line provided in each memory cell array to commonly connect with the plurality of memory cells, and a plurality of I/O (input/output) lines respectively connected with the plurality of memory cells of each memory cell array. The parallel bit test circuit for testing the plurality of memory cells in parallel bits comprises a comparator for comparing the data of the memory cells with an externally input data to produce a test signal applied to a data I/O terminal.
摘要翻译：提供了一种新颖的并行比特测试电路来测试半导体存储器件，其包括多个存储单元阵列，每个存储单元阵列具有多个存储器单元，每个存储单元阵列中提供的字线与多个存储器单元共同连接;以及分别与每个存储单元阵列的多个存储单元连接的多个I / O（输入/输出）线。用于以并行比特测试多个存储单元的并行比特测试电路包括比较器，用于将存储器单元的数据与外部输入数据进行比较，以产生施加到数据I / O端子的测试信号。

4. 发明授权

US5325334A Column redundancy circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的列冗余电路
公开(公告)号：US5325334A
公开(公告)日：1994-06-28
申请号：US14305
申请日：1993-02-05
申请人： Jae-Gu Roh , Yong-Sik Seok
发明人： Jae-Gu Roh , Yong-Sik Seok
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/808
摘要： A column redundancy circuit for a semiconductor memory device, e.g., a DRAM, which includes a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective. The column redundancy circuit includes a plurality of redundant columns, block selection control circuit which is programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of the memory blocks which contain the defective column, a column address decoder which is programmed to generate a second output signal in response to receipt of both the first output signal and a column address signal corresponding to the defective column, and, a redundant column driver circuit which is responsive to the second output signal for activating a predetermined one of the redundant columns, to thereby repair the defective column. In a preferred embodiment, the block selection control circuit and the column address decoder each include a plurality of fuses and are each programmed by means of a selected one or more of their fuses being blown, e.g., by use of a laser.
摘要翻译：一种用于半导体存储器件（例如DRAM）的列冗余电路，其包括由多个存储块构成的正常存储器阵列，每个存储器块由行和列的存储器单元组成，其中至少两个存储器块共享公共列，并且至少一个列是有缺陷的，在连接到被确定为有缺陷的至少一个存储单元的意义上。列冗余电路包括多个冗余列，块选择控制电路被编程为响应于接收到与包含缺陷列的一个或多个存储器块相对应的存储器块地址信号而产生第一输出信号，列地址解码器，其被编程为响应于接收到与缺陷列对应的第一输出信号和列地址信号两者而产生第二输出信号;以及冗余列驱动器电路，其响应于第二输出信号用于激活冗余列中的预定的一个，从而修复有缺陷的列。在优选实施例中，块选择控制电路和列地址解码器各自包括多个保险丝，并且各自通过例如通过使用激光而被熔断的所选择的一个或多个保险丝进行编程。

5. 发明授权

US6046624A Internal power supply generating circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的内部电源产生电路
公开(公告)号：US6046624A
公开(公告)日：2000-04-04
申请号：US988285
申请日：1997-12-10
申请人： Ga-pyo Nam , Yong-sik Seok , Hi-choon Lee
发明人： Ga-pyo Nam , Yong-sik Seok , Hi-choon Lee
IPC分类号： G11C11/413 , G05F1/46 , G05F1/56 , G05F3/24 , G11C5/14 , G11C11/407 , H02J3/38
CPC分类号： G05F1/465
摘要： An internal power supply generating circuit for a semiconductor memory device reduces fluctuations in the external power supply by reducing the rate at which a drive transistor is turned on and off. The circuit includes a drive transistor that generates an internal power signal by reducing the external power supply voltage responsive to a bias signal. A feedback loop generates the bias signal and slows down the rate at which the bias signal changes, thereby reducing the rate at which the drive transistor turns on and off. The feedback loop includes a comparator for comparing the internal power supply voltage to a reference voltage and a bias circuit having a pair of push-pull transistors for generating the bias signal responsive to the output of the comparator. To slow down the rate at which the bias signal changes, the bias circuit includes a resistor coupled in series with the transistors and/or a capacitor couple to the output terminal of the bias circuit. Alternatively, the bias circuit includes a third transistor coupled in series with the push-pull transistors. A voltage divider is coupled to the gate of the third transistor and the gate of one of the push-pull transistors to turn the third transistor on. The feedback loop optionally includes a delay circuit to prevent malfunctions caused by the differences in voltage associated with sensing the internal power supply voltage at remote locations on a memory device.
摘要翻译：用于半导体存储器件的内部电源产生电路通过降低驱动晶体管导通和关断的速率来减小外部电源的波动。电路包括驱动晶体管，其通过响应于偏置信号减小外部电源电压来产生内部功率信号。反馈环路产生偏置信号并降低偏置信号变化的速率，从而降低驱动晶体管导通和截止的速率。反馈环路包括用于将内部电源电压与参考电压进行比较的比较器和具有一对推挽晶体管的偏置电路，用于响应于比较器的输出产生偏置信号。为了减缓偏置信号变化的速率，偏置电路包括与晶体管串联耦合的电阻器和/或电容器耦合到偏置电路的输出端子。或者，偏置电路包括与推挽晶体管串联耦合的第三晶体管。分压器耦合到第三晶体管的栅极和其中一个推挽晶体管的栅极，以使第三晶体管导通。反馈环路可选地包括延迟电路，以防止由与感测存储器设备上的远程位置处的内部电源电压相关联的电压差引起的故障。

6. 发明授权

US5732029A Method and circuit for testing memory cells in semiconductor memory device 失效
标题翻译：用于测试半导体存储器件中的存储单元的方法和电路
公开(公告)号：US5732029A
公开(公告)日：1998-03-24
申请号：US650398
申请日：1996-05-20
申请人： Sang-Kil Lee , Yong-Sik Seok
发明人： Sang-Kil Lee , Yong-Sik Seok
IPC分类号： G11C11/401 , G11C29/00 , G11C29/24 , G11C29/34 , G11C7/00
CPC分类号： G11C29/808 , G11C29/24 , G11C29/781
摘要： A test control circuit and method of testing a memory cell in a semiconductor memory device. The test control circuit includes a memory cell array having a plurality of normal memory cells to store data on a semiconductor substrate and a plurality of redundancy memory cells to substitute for defective normal memory cells. Row and column redundancy fuse boxes include fuse elements to be electrically fused to enable row and column redundancy decoders for selecting rows and columns of the redundancy memory cells. A redundancy cell test signal generator generates, in response to a test signal applied to an extra line in the address bus, a master clock for testing the redundancy memory cell under the same mode as a test mode of the normal memory cell. A test controller provides an enable signal for selecting the redundancy memory cells of a memory array in response to logic levels of the master clock and an address signal applied during the redundancy memory cell test.
摘要翻译：一种测试半导体存储器件中的存储单元的测试控制电路和方法。测试控制电路包括具有多个正常存储器单元的存储单元阵列，以在半导体衬底上存储数据，以及多个冗余存储单元来代替有缺陷的正常存储单元。行和列冗余保险丝盒包括要电熔接的熔丝元件，以实现用于选择冗余存储器单元的行和列的行和列冗余解码器。冗余单元测试信号发生器响应于施加到地址总线中的额外线路的测试信号而产生用于在与正常存储器单元的测试模式相同的模式下测试冗余存储单元的主时钟。测试控制器提供用于响应于主时钟的逻辑电平和在冗余存储器单元测试期间施加的地址信号来选择存储器阵列的冗余存储单元的使能信号。

7. 发明授权

US5687128A Power supply voltage boosting circuit of semiconductor memory device 失效
标题翻译：半导体存储器件的电源升压电路
公开(公告)号：US5687128A
公开(公告)日：1997-11-11
申请号：US551005
申请日：1995-10-31
申请人： Jae-Hyeong Lee , Yong-Sik Seok
发明人： Jae-Hyeong Lee , Yong-Sik Seok
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C13/00
CPC分类号： G11C5/145 , G11C11/4074
摘要： An active power supply voltage boosting circuit for a semiconductor memory device according to the present invention causes operation of the active cycle boosted voltage generating circuit to elevate the level of the boosted power supply voltage V.sub.PP when the detected level of the boosted power supply voltage V.sub.PP is lower than a target voltage level. Thus, the boosted power supply voltage V.sub.PP can be stably maintained to the target voltage level. When the boosted power supply voltage V.sub.PP becomes higher than the target voltage level, generation of the boosted power supply voltage V.sub.PP is stopped, and as a result, unwanted consumption of the electrical current and also the damage to the semiconductor memory device by high voltage can be prevented.
摘要翻译：根据本发明的用于半导体存储器件的有源电源电压升压电路使检测到的升压电源电压VPP的电平为VPP时，主动周期升压电压产生电路的操作提升升压电源电压VPP的电平低于目标电压电平。因此，可以将升压电源电压VPP稳定地维持在目标电压电平。当升压电源电压VPP变得高于目标电压电平时，升压的电源电压VPP的产生被停止，结果，电流的不必要的消耗以及高电压对半导体存储器件的损坏被阻止

8. 发明授权

US5402378A Circuit for generating a clock signal to separate bit lines in a semiconductor memory device 失效
标题翻译：用于产生时钟信号以在半导体存储器件中分离位线的电路
公开(公告)号：US5402378A
公开(公告)日：1995-03-28
申请号：US972522
申请日：1992-11-06
申请人： Kyung-Youl Min , Yong-Sik Seok
发明人： Kyung-Youl Min , Yong-Sik Seok
IPC分类号： G11C11/417 , G11C5/14 , G11C7/12 , G11C7/18 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , G11C7/00
CPC分类号： G11C7/12 , G11C5/14 , G11C7/18 , G11C7/22
摘要： A semiconductor memory device using a low level supply voltage has separation gates for isolating adjacent bit lines. The device may be constructed with a circuit for receiving a high voltage supplied by a high voltage generator resident upon the chip so as to provide the separation gates with a voltage increased at least by the amount of the threshold voltage of the separation gates over the supply voltage.
摘要翻译：使用低电平电源电压的半导体存储器件具有用于隔离相邻位线的分离栅极。该器件可以构造有用于接收由驻留在芯片上的高电压发生器提供的高电压的电路，以便为分离门提供至少增加电源上的分离门的阈值电压的量的电压电压。

9. 发明授权

US5293559A Semiconductor memory device having netlike power supply lines 失效
标题翻译：具有网状电源线的半导体存储器件
公开(公告)号：US5293559A
公开(公告)日：1994-03-08
申请号：US770241
申请日：1991-10-03
申请人： Hyun-Soo Kim , Yong-Sik Seok
发明人： Hyun-Soo Kim , Yong-Sik Seok
IPC分类号： G11C5/14 , H01L27/10
CPC分类号： G11C5/14
摘要： A semiconductor memory device for minimizing the resistance attendant on reaching as far as each sense amplifier connected to a memory cell. A first plurality of power supply lines are alternatively disposed between column select lines which is formed over a plurality of lines of semiconductor memory device in a column direction. The first plurality of power supply lines the first plurality of ground lines are connected to a second plurality of power supply lines and a second plurality of ground lines which are disposed under the column select lines in a row direction, to thereby provide a netlike power supply structure. Consequently, the operating speed of a chip is improved by minimizing the resistance attendant on reaching as far as the sense amplifiers connected to each memory cell and the efficiency of the semiconductor memory device is greatly promoted by suppressing a coupling phenomenon caused between the column select lines.
摘要翻译：一种半导体存储器件，用于使连接到存储器单元的每个读出放大器达到的电阻最小化。交替地，第一组多个电源线设置在列列方向上形成在多条半导体存储器件行上的列选择线之间。所述第一多个电源线与所述第二多个电源线连接，并且所述第二多个接地线设置在所述列选择线的行方向下方，从而提供网状电源结构体。因此，通过使连接到每个存储单元的感测放大器达到的电阻最小化来提高芯片的工作速度，并且通过抑制在列选择线之间引起的耦合现象来极大地促进半导体存储器件的效率。

10. 发明授权

US5103166A Semiconductor integrated circuit chip having an identification circuit therein 失效
标题翻译：具有标识电路的半导体集成电路芯片
公开(公告)号：US5103166A
公开(公告)日：1992-04-07
申请号：US578284
申请日：1990-09-06
申请人： Dong-su Jeon , Yong-sik Seok
发明人： Dong-su Jeon , Yong-sik Seok
IPC分类号： G01R31/28 , G06F11/00 , G11C5/00 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/12 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/544 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/0203 , G06F11/006 , G11C5/04 , G11C7/1045 , H01L23/544 , G11C2029/4402 , G11C29/12 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002
摘要： A semiconductor integrated circuit chip has an identification circuit connected between a power voltage supply terminal and one of the input terminals of the chip. The identification circuity includes a voltage limiter to limit the input potential difference between the power voltage supply terminal and the input terminal to a predetermined voltage level. The identification circuit further includes an option device connected to the voltage limiter to provide identification information of the chip. According to the identification circuit, chip identification testing may be achieved with existing input/output and power supply terminals, thereby eliminating the need for extra test and diagnosis pins or additional identification equipment employed during testing.
摘要翻译：半导体集成电路芯片具有连接在电源电压端子和芯片的一个输入端子之间的识别电路。识别电路包括电压限制器，以将电源电压端子和输入端子之间的输入电位差限制到预定电压电平。识别电路还包括连接到限压器的选件装置，以提供芯片的识别信息。根据识别电路，可以利用现有的输入/输出和电源端子来实现芯片识别测试，从而不需要在测试期间使用的额外的测试和诊断引脚或附加的识别设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式