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1. 发明授权

US5103166A Semiconductor integrated circuit chip having an identification circuit therein 失效
标题翻译：具有标识电路的半导体集成电路芯片
公开(公告)号：US5103166A
公开(公告)日：1992-04-07
申请号：US578284
申请日：1990-09-06
申请人： Dong-su Jeon , Yong-sik Seok
发明人： Dong-su Jeon , Yong-sik Seok
IPC分类号： G01R31/28 , G06F11/00 , G11C5/00 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/12 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/544 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/0203 , G06F11/006 , G11C5/04 , G11C7/1045 , H01L23/544 , G11C2029/4402 , G11C29/12 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002
摘要： A semiconductor integrated circuit chip has an identification circuit connected between a power voltage supply terminal and one of the input terminals of the chip. The identification circuity includes a voltage limiter to limit the input potential difference between the power voltage supply terminal and the input terminal to a predetermined voltage level. The identification circuit further includes an option device connected to the voltage limiter to provide identification information of the chip. According to the identification circuit, chip identification testing may be achieved with existing input/output and power supply terminals, thereby eliminating the need for extra test and diagnosis pins or additional identification equipment employed during testing.
摘要翻译：半导体集成电路芯片具有连接在电源电压端子和芯片的一个输入端子之间的识别电路。识别电路包括电压限制器，以将电源电压端子和输入端子之间的输入电位差限制到预定电压电平。识别电路还包括连接到限压器的选件装置，以提供芯片的识别信息。根据识别电路，可以利用现有的输入/输出和电源端子来实现芯片识别测试，从而不需要在测试期间使用的额外的测试和诊断引脚或附加的识别设备。

2. 发明授权

US5590079A Wafer burn-in test circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的晶片老化测试电路
公开(公告)号：US5590079A
公开(公告)日：1996-12-31
申请号：US474158
申请日：1995-06-07
申请人： Jae-Hyeong Lee , Yong-sik Seok
发明人： Jae-Hyeong Lee , Yong-sik Seok
IPC分类号： G11C11/413 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G01R31/2856 , G11C11/401
摘要： A wafer burn-in test circuit for sensing a defective cell of a semiconductor memory device having a plurality of memory cells connected to a word line and a row decoder for selecting the word line. The burn-in test includes a word line driver circuit having an input coupled to a row decoding signal generated by the row decoder, and an ouput coupled to the word line, a control circuit having a first input coupled to a burn-in voltage signal, and a second input coupled to a control signal, and an electrical line connected between the word line driver circuit and the control circuit. In a normal mode of operation, the word line driver circuit is responsive to the row decoding signal for raising the word line to an enable voltage level. In a burn-in test mode of operation, the control circuit is responsive to the control signal for applying a burn-in voltage to the word line via the electrical line and the word line driver circuit.
摘要翻译：一种用于感测具有连接到字线的多个存储单元的半导体存储器件的缺陷单元的晶片老化测试电路以及用于选择字线的行解码器。老化测试包括字线驱动器电路，其具有耦合到由行解码器产生的行解码信号的输入和耦合到字线的输出，控制电路具有耦合到老化电压信号的第一输入以及耦合到控制信号的第二输入，以及连接在字线驱动电路和控制电路之间的电线。在正常操作模式下，字线驱动电路响应行解码信号，将字线升高到使能电压电平。在老化测试操作模式中，控制电路响应于经由电线和字线驱动器电路向字线施加老化电压的控制信号。

3. 发明授权

US6046624A Internal power supply generating circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的内部电源产生电路
公开(公告)号：US6046624A
公开(公告)日：2000-04-04
申请号：US988285
申请日：1997-12-10
申请人： Ga-pyo Nam , Yong-sik Seok , Hi-choon Lee
发明人： Ga-pyo Nam , Yong-sik Seok , Hi-choon Lee
IPC分类号： G11C11/413 , G05F1/46 , G05F1/56 , G05F3/24 , G11C5/14 , G11C11/407 , H02J3/38
CPC分类号： G05F1/465
摘要： An internal power supply generating circuit for a semiconductor memory device reduces fluctuations in the external power supply by reducing the rate at which a drive transistor is turned on and off. The circuit includes a drive transistor that generates an internal power signal by reducing the external power supply voltage responsive to a bias signal. A feedback loop generates the bias signal and slows down the rate at which the bias signal changes, thereby reducing the rate at which the drive transistor turns on and off. The feedback loop includes a comparator for comparing the internal power supply voltage to a reference voltage and a bias circuit having a pair of push-pull transistors for generating the bias signal responsive to the output of the comparator. To slow down the rate at which the bias signal changes, the bias circuit includes a resistor coupled in series with the transistors and/or a capacitor couple to the output terminal of the bias circuit. Alternatively, the bias circuit includes a third transistor coupled in series with the push-pull transistors. A voltage divider is coupled to the gate of the third transistor and the gate of one of the push-pull transistors to turn the third transistor on. The feedback loop optionally includes a delay circuit to prevent malfunctions caused by the differences in voltage associated with sensing the internal power supply voltage at remote locations on a memory device.
摘要翻译：用于半导体存储器件的内部电源产生电路通过降低驱动晶体管导通和关断的速率来减小外部电源的波动。电路包括驱动晶体管，其通过响应于偏置信号减小外部电源电压来产生内部功率信号。反馈环路产生偏置信号并降低偏置信号变化的速率，从而降低驱动晶体管导通和截止的速率。反馈环路包括用于将内部电源电压与参考电压进行比较的比较器和具有一对推挽晶体管的偏置电路，用于响应于比较器的输出产生偏置信号。为了减缓偏置信号变化的速率，偏置电路包括与晶体管串联耦合的电阻器和/或电容器耦合到偏置电路的输出端子。或者，偏置电路包括与推挽晶体管串联耦合的第三晶体管。分压器耦合到第三晶体管的栅极和其中一个推挽晶体管的栅极，以使第三晶体管导通。反馈环路可选地包括延迟电路，以防止由与感测存储器设备上的远程位置处的内部电源电压相关联的电压差引起的故障。

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