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1. 发明申请

US20150155024A1 MAGNETIC MEMORY DEVICES INCLUDING SHARED LINES 有权
标题翻译：包含共享线的磁记录设备
公开(公告)号：US20150155024A1
公开(公告)日：2015-06-04
申请号：US14448717
申请日：2014-07-31
申请人： Bo-Young SEO , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
发明人： Bo-Young SEO , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659
摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
摘要翻译：磁存储器件包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。还描述了相关系统和操作方法。

2. 发明授权

US08110873B2 High voltage transistor 失效
标题翻译：高压晶体管
公开(公告)号：US08110873B2
公开(公告)日：2012-02-07
申请号：US12339448
申请日：2008-12-19
申请人： Sung-Gon Choi , Hee-Seog Jeon
发明人： Sung-Gon Choi , Hee-Seog Jeon
IPC分类号： H01L21/76
CPC分类号： H01L29/0847 , H01L21/76895 , H01L29/0692 , H01L29/402 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7831 , H01L29/7833 , H01L29/7835
摘要： A high voltage transistor that includes a substrate where an active region is defined, a first impurity region and a second impurity region in the active region and a third impurity region between the first and second impurity regions, and a first gate electrode on the active region between the first impurity region and the third impurity region and a second gate electrode on the active region between the second impurity region and the third impurity region.
摘要翻译：一种高电压晶体管，包括限定有源区的衬底，所述有源区中的第一杂质区和第二杂质区以及所述第一和第二杂质区之间的第三杂质区，以及所述有源区上的第一栅电极在第一杂质区域和第三杂质区域之间的有源区域上的第二栅电极和第二杂质区域之间的有源区域上的第二栅电极。

3. 发明申请

US20110038210A1 Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其形成和读取方法
公开(公告)号：US20110038210A1
公开(公告)日：2011-02-17
申请号：US12912517
申请日：2010-10-26
申请人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
发明人： Yong-Kyu Lee , Jeong-Uk Han , Hee-Seog Jeon , Jung-Ho Moon , Soung-Youb Ha
IPC分类号： G11C16/26 , G11C16/04 , G11C16/30
CPC分类号： G11C16/0433 , G11C16/26 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
摘要翻译：在EEPROM单元中读取数据的方法中，用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。第一电压被施加到存储晶体管的感测线。大于第一电压的第二电压被施加到选择晶体管的字线。将通过EEPROM单元的电流与预定的参考电流进行比较，以读取存储在EEPROM单元中的数据。可以在擦除状态下增加EEPROM单元的通电池电流，并且可以容易地区分单元中的数据。

4. 发明申请

US20100265765A1 Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same 有权
标题翻译：减少程序干扰的非易失性半导体存储器件及其编程方法
公开(公告)号：US20100265765A1
公开(公告)日：2010-10-21
申请号：US12662431
申请日：2010-04-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Kwang-Tae Kim , Ji-Hoon Park , Myung-Jo Chun
发明人： Bo-Young Seo , Hee-Seog Jeon , Kwang-Tae Kim , Ji-Hoon Park , Myung-Jo Chun
IPC分类号： G11C16/02 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/24
摘要： A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.
摘要翻译：提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

5. 发明授权

US07638387B2 Mask ROM and method of fabricating the same 有权
标题翻译：掩模ROM及其制造方法
公开(公告)号：US07638387B2
公开(公告)日：2009-12-29
申请号：US11823381
申请日：2007-06-27
申请人： Yong-Kyu Lee , Hee-Seog Jeon , Jeong-Uk Han , Young-Ho Kim , Myung-Jo Chun
发明人： Yong-Kyu Lee , Hee-Seog Jeon , Jeong-Uk Han , Young-Ho Kim , Myung-Jo Chun
IPC分类号： H01L21/8234
CPC分类号： H01L27/1021
摘要： A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.
摘要翻译：掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示第二种类型的存储单元。多个第二导电线中的每一个形成在二极管的列上。

6. 发明授权

US07602008B2 Split gate non-volatile memory devices and methods of forming the same 失效
标题翻译：分闸非易失性存储器件及其形成方法
公开(公告)号：US07602008B2
公开(公告)日：2009-10-13
申请号：US11957037
申请日：2007-12-14
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L27/115
CPC分类号： H01L29/7887 , H01L29/66825
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

7. 发明授权

US07531410B2 Semiconductor flash memory device and method of fabricating the same 失效
标题翻译：半导体闪存器件及其制造方法
公开(公告)号：US07531410B2
公开(公告)日：2009-05-12
申请号：US11648057
申请日：2006-12-29
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Seung-Jin Yang , Hyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Seung-Jin Yang , Hyok-Ki Kwon
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42336
摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.
摘要翻译：半导体闪存器件。闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。栅极绝缘膜介于浮栅电极和半导体衬底之间。控制栅电极设置在浮栅电极上。浮栅电极包括与凹部的倾斜侧相邻的突起。

8. 发明授权

US07492000B2 Self-aligned split-gate nonvolatile memory structure and a method of making the same 有权
标题翻译：自对准分离门非易失性存储器结构及其制造方法
公开(公告)号：US07492000B2
公开(公告)日：2009-02-17
申请号：US11444369
申请日：2006-06-01
申请人： Hee Seog Jeon , Seung Beom Yoon , Yong Tae Kim
发明人： Hee Seog Jeon , Seung Beom Yoon , Yong Tae Kim
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the split-gate elements. Each control gate includes a projecting portion that extends over at least a portion of the associated floating gate with the size of the projecting portion being determined by a first sacrificial polysilicon spacer that, when removed, produces a concave region in an intermediate insulating structure. The control gate is then formed as a polysilicon spacer adjacent the intermediate insulating structure, the portion of the spacer extending into the concave region determining the dimension and spacing of the projecting portion and the thickness of the interpoly oxide (IPO) separating the upper portions of the split-gate electrodes thereby providing improved performance and manufacturability.
摘要翻译：提供了具有自对准浮动栅极的非易失性分裂栅极存储器单元以及用于制造这样的存储单元的控制栅极结构和示例性工艺，其提供了分离栅极元件的相对长度和间隔的改进的尺寸控制。每个控制门包括突出部分，该突出部分在相关联的浮动栅极的至少一部分上延伸，突出部分的尺寸由第一牺牲多晶硅间隔物确定，当被去除时，其在中间绝缘结构中产生凹入区域。然后，控制栅极形成为与中间绝缘结构相邻的多晶硅间隔物，间隔物的延伸到凹区中的部分确定突出部分的尺寸和间距以及分离上部的多晶硅氧化物（IPO）的厚度因此分裂栅电极提供了改进的性能和可制造性。

9. 发明申请

US20070111444A1 Method of manufacturing split gate type nonvolatile memory device 审中-公开
标题翻译：分闸式非易失性存储装置的制造方法
公开(公告)号：US20070111444A1
公开(公告)日：2007-05-17
申请号：US11648566
申请日：2007-01-03
申请人： Hee-seog Jeon , Seung-beom Yoon
发明人： Hee-seog Jeon , Seung-beom Yoon
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.
摘要翻译：一种制造其中通过自对准工艺形成控制栅极的分离栅型非易失性半导体存储器件的方法。

10. 发明授权

US07176085B2 Method of manufacturing split gate type nonvolatile memory device 失效
公开(公告)号：US07176085B2
公开(公告)日：2007-02-13
申请号：US11262767
申请日：2005-11-01
申请人： Hee-seog Jeon , Seung-beom Yoon
发明人： Hee-seog Jeon , Seung-beom Yoon
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process.

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