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1. 发明授权

US08519802B2 Pulse width modulation driving IC and pulse width modulation output signal generating method 有权
标题翻译：脉宽调制驱动IC和脉宽调制输出信号产生方法
公开(公告)号：US08519802B2
公开(公告)日：2013-08-27
申请号：US13172816
申请日：2011-06-29
申请人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
发明人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.
摘要翻译：本发明公开了一种脉宽调制驱动IC。脉宽调制驱动IC包括用于接收第一信号的第一引脚，用于接收第二信号的第二引脚，用于将第一信号与参考电压进行比较的比较单元，以产生指示操作模式的比较结果以及输出单元，用于根据第一信号，第二信号和比较结果输出脉宽调制输出信号。

2. 发明授权

US08243629B2 Methods and apparatus for selecting between an ad-hoc conference mode and an infrastructure supported conference mode 有权
标题翻译：用于在自组会议模式和基础设施支持的会议模式之间进行选择的方法和装置
公开(公告)号：US08243629B2
公开(公告)日：2012-08-14
申请号：US12506697
申请日：2009-07-21
申请人： Patrick Stephen , Greg Dykes , Richard Joyner , Yi-Cheng Liu , Edgardo Promenzio
发明人： Patrick Stephen , Greg Dykes , Richard Joyner , Yi-Cheng Liu , Edgardo Promenzio
IPC分类号： H04L12/16
CPC分类号： H04W76/40 , H04W36/30
摘要： Devices that are enabled to communicate with each other via an ad hoc conference mode and an infrastructure supported conference mode, are provided with processing capabilities that can allow them to evaluate one or more resources required to support an ad hoc conference communication session and/or one or more quality metrics associated with the ad hoc conference communication session, and determine whether one or more resources or metrics are outside optimal operating parameters. If so, the processing logic can initiate a transition from the ad hoc conference communication session to an infrastructure supported conference communication session hosted at a conference server. This way, the devices can drop the ad hoc conference communication session when one or more of the resources or metrics are outside optimal operating parameters, so that one of the devices does not need to mix communication information streams (CISs) from the devices, generate a plurality of conferenced communication information streams (CCISs), and transmit a unique one of the conferenced communication information streams (CCISs) to the other devices.
摘要翻译：能够经由特别会议模式和基础设施支持的会议模式相互通信的设备被提供有处理功能，其可以允许他们评估支持特别会议通信会话所需的一个或多个资源和/或一个或更多与质量会议通信会话相关联的质量度量，以及确定一个或多个资源或度量是否在最佳操作参数之外。如果是这样，则处理逻辑可以启动从特设会议通信会话转移到在会议服务器上托管的基础设施支持的会议通信会话。这样，当一个或多个资源或指标在最佳操作参数之外时，设备可以丢弃自组织会议通信会话，使得设备中的一个不需要混合来自设备的通信信息流（CIS），产生多个会议通信信息流（CCIS），并且将另一个会议通信信息流（CCIS）中的唯一一个发送到其他设备。

3. 发明授权

US08058133B2 Method of fabrication of metal oxide semiconductor field effect transistor 有权
标题翻译：金属氧化物半导体场效应晶体管的制造方法
公开(公告)号：US08058133B2
公开(公告)日：2011-11-15
申请号：US12273517
申请日：2008-11-18
申请人： Chen-Hua Tsai , Bang-Chiang Lan , Yu-Hsin Lin , Yi-Cheng Liu , Cheng-Tzung Tsai
发明人： Chen-Hua Tsai , Bang-Chiang Lan , Yu-Hsin Lin , Yi-Cheng Liu , Cheng-Tzung Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L29/6656 , H01L29/66636 , H01L29/7834 , Y10S438/931 , Y10S438/933 , Y10S438/938
摘要： A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.
摘要翻译：制造金属氧化物半导体场效应晶体管的方法包括首先提供其上形成有栅极结构的衬底。之后，去除衬底的一部分以在栅极结构的两端形成衬底中的第一凹槽。另外，源极/漏极延伸层沉积在第一凹槽中，并且在栅极结构的两端形成多个间隔物。随后，去除源极/漏极延伸部分和衬底的一部分以在源极/漏极延伸部中形成第二凹部，并且在衬垫的外部形成衬底的一部分。另外，源极/漏极层沉积在第二凹部中。由于源极/漏极延伸部和源极/漏极层具有特定的材料和结构，因此提高了沟道效应，提高了金属氧化物半导体场效应晶体管的效率。

4. 发明授权

US07985653B2 Semiconductor chip with coil element over passivation layer 有权
标题翻译：半导体芯片具有钝化层上的线圈元件
公开(公告)号：US07985653B2
公开(公告)日：2011-07-26
申请号：US12276419
申请日：2008-11-24
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： H01L21/20 , H01L21/8222 , H01L21/8234 , H01L21/4763 , H01L21/8238
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
摘要翻译：一种用于制造电路部件的方法包括提供半导体衬底，在所述半导体衬底上的第一线圈，在所述第一线圈上方的钝化层; 以及在所述钝化层上并在所述第一线圈上方沉积第二线圈。所述第二线圈可以通过在所述钝化层上形成第一金属层而形成，在所述第一金属层上形成图案限定层，所述图案限定层中的第一开口暴露所述第一金属层，在所述第一金属层上形成第二金属层由所述第一开口暴露的金属层，去除所述图案限定层，以及去除不在所述第二金属层下方的所述第一金属层。

5. 发明申请

US20070133439A1 Method and apparatus to facilitate transferring chairmanship of an ad-hoc conference call 审中-公开
标题翻译：便利转移特设电话会议主席的方法和装置
公开(公告)号：US20070133439A1
公开(公告)日：2007-06-14
申请号：US11301143
申请日：2005-12-12
申请人： Edgardo Promenzio , Yi-Cheng Liu , Rajendra Panchal
发明人： Edgardo Promenzio , Yi-Cheng Liu , Rajendra Panchal
IPC分类号： H04Q11/00
CPC分类号： H04Q11/00 , H04Q2213/13178 , H04Q2213/1324 , H04Q2213/1328
摘要： One detects (101) an indication from an initiator of a presently supported ad-hoc conference call who seeks to transfer chairmanship of the presently supported ad-hoc conference call to another conference call participant. The chairmanship is then transferred (102) to this other participant to thereby provide a presently supported ad-hoc conference call having a transferred chairman.
摘要翻译：一个检测（101）来自目前支持的特设电话会议的发起者的指示，其寻求将当前支持的自组织电话会议的主席转移给另一个电话会议参与者。然后将主席权转让给另一参与者，从而提供目前支持的转交主席的特设电话会议。

6. 发明申请

US20060286730A1 Semiconductor structure and method for forming thereof 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20060286730A1
公开(公告)日：2006-12-21
申请号：US11154377
申请日：2005-06-15
申请人： Yi-Cheng Liu (Alex Liu) , Jiunn-Ren Hwang , Wei-Tsun Shiau
发明人： Yi-Cheng Liu (Alex Liu) , Jiunn-Ren Hwang , Wei-Tsun Shiau
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over a sidewall of the gate. Then, a source/drain trench is formed in the substrate at two sides of the gate respectively. Next, an outermost offspacer of the offspacers is removed to expose a flat surface on a surface of the substrate. Thereafter, the source/drain trenches are filled to form a source/drain region. Then, a lightly doped drain (LDD) region is formed in a portion of the substrate under the flat surface.
摘要翻译：提供半导体结构和形成半导体结构的方法。本发明的半导体结构的形成方法可以包括以下步骤。首先，提供衬底，其中在衬底上形成栅极，并且在栅极的侧壁上方形成多个脱离层。然后，在栅极的两侧分别在衬底中形成源极/漏极沟槽。接下来，除去离子的最外层的隔离物以露出基底表面上的平坦表面。此后，填充源极/漏极沟槽以形成源极/漏极区域。然后，在平坦表面下的基板的一部分中形成轻掺杂漏极（LDD）区域。

7. 发明申请

US20060263727A1 Semiconductor chip with coil element over passivation layer 有权
公开(公告)号：US20060263727A1
公开(公告)日：2006-11-23
申请号：US11434861
申请日：2006-05-17
申请人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
发明人： Wen-Chieh Lee , Mou-Shiung Lin , Chien-Kang Chou , Yi-Cheng Liu , Chiu-Ming Chou , Jin-Yuan Lee
IPC分类号： G03C5/00
CPC分类号： H01L23/3114 , H01L23/5227 , H01L23/525 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05624 , H01L2224/13 , H01L2224/13099 , H01L2224/48463 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10329 , H01L2924/1305 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2224/45099 , H01L2924/00
摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

8. 发明授权

US07135365B2 Method of manufacturing MOS transistors 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US07135365B2
公开(公告)日：2006-11-14
申请号：US10907342
申请日：2005-03-30
申请人： Yi-Cheng Liu , Wen-Chi Chen , Tzu-Yun Chang , Bang-Chiang Lan , Cheng-Tung Huang , Wei-Tsun Shiau , Kuan-Yang Liao
发明人： Yi-Cheng Liu , Wen-Chi Chen , Tzu-Yun Chang , Bang-Chiang Lan , Cheng-Tung Huang , Wei-Tsun Shiau , Kuan-Yang Liao
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823864 , H01L21/823807 , H01L21/823814
摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.
摘要翻译：首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。然后在基板和多个栅极结构上形成高拉伸薄膜。随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

9. 发明申请

US20060099763A1 METHOD OF MANUFACTURING SEMICONDUCTOR MOS TRANSISTOR DEVICE 审中-公开
公开(公告)号：US20060099763A1
公开(公告)日：2006-05-11
申请号：US10904210
申请日：2004-10-28
申请人： Yi-Cheng Liu , Jiunn-Ren Hwang , Wei-Tsun Shiau , Cheng-Tung Huang , Kuan-Yang Liao
发明人： Yi-Cheng Liu , Jiunn-Ren Hwang , Wei-Tsun Shiau , Cheng-Tung Huang , Kuan-Yang Liao
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.

10. 发明申请

US20120274411A1 Pulse Width Modulation Driving IC and Pulse Width Modulation Output Signal Generating Method 有权
标题翻译：脉宽调制驱动IC和脉宽调制输出信号产生方法
公开(公告)号：US20120274411A1
公开(公告)日：2012-11-01
申请号：US13172816
申请日：2011-06-29
申请人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
发明人： Chia-Tai Yang , Yi-Cheng Liu , Ching-Sheng Li , Kun-Min Chen , Ching-Shan Lu
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result.
摘要翻译：本发明公开了一种脉宽调制驱动IC。脉宽调制驱动IC包括用于接收第一信号的第一引脚，用于接收第二信号的第二引脚，用于将第一信号与参考电压进行比较的比较单元，以产生指示操作模式的比较结果以及输出单元，用于根据第一信号，第二信号和比较结果输出脉宽调制输出信号。

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