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1. 发明授权

US08421660B1 Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance 有权
标题翻译：可配置的级联Σ-Δ模数转换器（ADC），用于调节功率和性能
公开(公告)号：US08421660B1
公开(公告)日：2013-04-16
申请号：US13304526
申请日：2011-11-25
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Andrea Baschirotto
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Andrea Baschirotto
IPC分类号： H03M3/00
CPC分类号： H03M3/392 , H03M3/414
摘要： A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.
摘要翻译：级联的Σ-Δ调制器具有多个调制器环路，其具有一组或两组积分器，加法器和定标器，以及产生回路输出的量化器。对每个环路输入多路复用器，从一个先前的循环中选择一个总体输入或一个环路输出，使调制器回路串联级联或单独运行。在每个调制器环路之后，滤波器配置的多路复用器选择该环路的输出或来自任何先前循环的回路输出或零。每个过滤器配置的多路复用器驱动输入到修改后的CIC过滤器。修改的CIC滤波器具有接收第一滤波器配置多路复用器输出的初始延迟级，以及每个接收连续的滤波器配置多路复用器输出的连续积分器级。改进的CIC滤波器是数字变换滤波器和级联积分器（CIC） - 滤波器（Cascaded-Integrator-Comb，CIC）滤波器的组合。调制解调器环路已经掉电，用于低性能配置或级联在一起以实现更高性能的配置。

2. 发明授权

US08416107B1 Charge compensation calibration for high resolution data converter 有权
标题翻译：高分辨率数据转换器的充电补偿校准
公开(公告)号：US08416107B1
公开(公告)日：2013-04-09
申请号：US13247119
申请日：2011-09-28
申请人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
发明人： Kam Chuen Wan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kwai Chi Chan
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译：校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容复制为终端电容，并且上下组之间的中间电容也被复制作为替代电容器。在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。温度计值反转到X阵列，但在Y阵列上保持不变。测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。

3. 发明授权

US08258864B1 Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权
标题翻译：具有自动调零功能的超低压多级高速CMOS比较器
公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译：前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。可以添加Kickback电荷隔离晶体管用于电荷隔离。输出也可以通过均衡的传输门来均衡。由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。

4. 发明申请

US20130141264A1 REDUCED RESIDUAL OFFSET SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER (ADC) WITH CHOPPER TIMING AT END OF INTEGRATING PHASE BEFORE TRAILING EDGE 有权
标题翻译：减少残留偏移SIGMA DELTA模拟数字转换器（ADC）在跟踪边缘之前的整合阶段结束时的切换时序
公开(公告)号：US20130141264A1
公开(公告)日：2013-06-06
申请号：US13308737
申请日：2011-12-01
申请人： Ho Ming (Karen) WAN , Yat To (William) WONG , Kwai Chi CHAN
发明人： Ho Ming (Karen) WAN , Yat To (William) WONG , Kwai Chi CHAN
IPC分类号： H03M3/02 , H03M1/12
CPC分类号： H03M3/34 , H03M3/43 , H03M3/454
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译：模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。

5. 发明授权

US08421658B1 Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC) 有权
标题翻译：在逐次逼近寄存器模数转换器（SAR-ADC）中，在先前的转换周期内对两个校准值进行并行流水线计算，
公开(公告)号：US08421658B1
公开(公告)日：2013-04-16
申请号：US13304346
申请日：2011-11-24
申请人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
发明人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/1047 , H03M1/468
摘要： A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
摘要翻译：逐次近似寄存器模数转换器（SAR-ADC）预测在未来周期中使用的补偿值。补偿值用于校准Y侧电容器阵列中的电容器，以补偿二进制加权的X侧电容器阵列中的电容误差。两个计算引擎预先计算下一个要转换的位的预测0和预测-1补偿值。在比较器确定当前位的当前周期结束时，比较器还控制多路复用器来选择两个预测补偿值之一。因此，补偿值在下一位循环开始时可用，消除了长时间的计算延迟。在校准期间计算要转换的第一位的补偿值，例如MSB。其他位的补偿值依赖于数据。在校准期间累积校准值，以生成要转换的第一个位的第一个转换补偿值。

6. 发明申请

US20100164770A1 MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING 有权
标题翻译：具有偏移取消电容器的多级比较器，用于高速低增益比较和高增益自动调零的二次差分输入
公开(公告)号：US20100164770A1
公开(公告)日：2010-07-01
申请号：US12347113
申请日：2008-12-31
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Kwok Kuen Kwong
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Kwok Kuen Kwong
IPC分类号： H03M1/12 , H03M1/00 , H03F3/217
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译：模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。最后一个阶段向SAR提供比较信号。每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。双输入差分放大器有两对差分输入。辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。在放大阶段，初级对通过输入开关连接到级输入。由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。在放大期间，双输入差分放大器中的电流吸收器被调高。

7. 发明授权

US07710094B1 Current-mode-controlled current sensor circuit for power switching converter 有权
标题翻译：用于电源开关变换器的电流模式控制电流传感器电路
公开(公告)号：US07710094B1
公开(公告)日：2010-05-04
申请号：US12333979
申请日：2008-12-12
申请人： Yat To William Wong , Xiao Fei Kuang , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Xiao Fei Kuang , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： G05F1/00 , G05F3/02 , G05F3/16
CPC分类号： H02M3/156 , G01R19/0092 , H02M2001/0009
摘要： A power converter has a power transistor driving a power current through an inductor to provide a controlled power-supply voltage. The power transistor is on during a first state but off during a second state when a sink transistor reduces the power current through the inductor. Both voltage sensing of the power-supply voltage and current sensing at the power transistor provide feedback to control the amount of time that the first state is active, and thus control the power current. Current sensing is provided by a smaller minor transistor in parallel with the power transistor. The minor transistor turns on after the power transistor to reduce disturbance spikes. Switches connect sources of the power and mirror transistors to an amplifier that drives a sensing transistor. The sensing transistor generates a sensing voltage from the mirror transistor source. During the second state the amplifier's inputs are equalized to provide fast response.
摘要翻译：功率转换器具有驱动通过电感器的功率电流以提供受控的电源电压的功率晶体管。功率晶体管在第一状态期间导通，而在第二状态期间，当晶体管晶体管降低通过电感器的功率电流时，功率晶体管截止。在功率晶体管处的电源电压和电流感测的两个电压检测提供反馈以控制第一状态是有效的时间量，从而控制功率电流。电流感测由与功率晶体管并联的较小次级晶体管提供。次晶体管在功率晶体管之后导通，以减少干扰尖峰。将电源和镜像晶体管的源极连接到驱动感测晶体管的放大器。感测晶体管产生来自反射镜晶体管源的感测电压。在第二状态期间，放大器的输入被均衡以提供快速响应。

8. 发明授权

US08471744B1 Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge 有权
标题翻译：减少残差偏移Σ-Δ模数转换器（ADC），在后沿积分相位结束时具有斩波定时
公开(公告)号：US08471744B1
公开(公告)日：2013-06-25
申请号：US13308737
申请日：2011-12-01
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan
IPC分类号： H03M3/00
CPC分类号： H03M3/34 , H03M3/43 , H03M3/454
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译：模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。

9. 发明申请

US20130076546A1 CHARGE COMPENSATION CALIBRATION FOR HIGH RESOLUTION DATA CONVERTER 有权
标题翻译：高分辨率数据转换器的电荷补偿校准
公开(公告)号：US20130076546A1
公开(公告)日：2013-03-28
申请号：US13247119
申请日：2011-09-28
申请人： Kam Chuen WAN , Yat To (William) WONG , Ho Ming (Karen) WAN , Kwai Chi CHAN
发明人： Kam Chuen WAN , Yat To (William) WONG , Ho Ming (Karen) WAN , Kwai Chi CHAN
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译：校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容器被复制为终端电容器，并且上下组之间的中间电容器也被重复作为替代电容器。在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。温度计值反转到X阵列，但在Y阵列上保持不变。测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。

10. 发明授权

US07999512B2 Single-power-transistor battery-charging circuit using voltage-boosted clock 有权
标题翻译：使用升压时钟的单功率晶体管电池充电电路
公开(公告)号：US07999512B2
公开(公告)日：2011-08-16
申请号：US12336514
申请日：2008-12-16
申请人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
发明人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。

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