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1. 发明授权

US08421658B1 Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC) 有权
标题翻译：在逐次逼近寄存器模数转换器（SAR-ADC）中，在先前的转换周期内对两个校准值进行并行流水线计算，
公开(公告)号：US08421658B1
公开(公告)日：2013-04-16
申请号：US13304346
申请日：2011-11-24
申请人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
发明人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/1047 , H03M1/468
摘要： A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
摘要翻译：逐次近似寄存器模数转换器（SAR-ADC）预测在未来周期中使用的补偿值。补偿值用于校准Y侧电容器阵列中的电容器，以补偿二进制加权的X侧电容器阵列中的电容误差。两个计算引擎预先计算下一个要转换的位的预测0和预测-1补偿值。在比较器确定当前位的当前周期结束时，比较器还控制多路复用器来选择两个预测补偿值之一。因此，补偿值在下一位循环开始时可用，消除了长时间的计算延迟。在校准期间计算要转换的第一位的补偿值，例如MSB。其他位的补偿值依赖于数据。在校准期间累积校准值，以生成要转换的第一个位的第一个转换补偿值。

2. 发明授权

US07741981B1 Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC 有权
标题翻译：双用比较器/运算放大器用作逐次逼近ADC和DAC
公开(公告)号：US07741981B1
公开(公告)日：2010-06-22
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/00
CPC分类号： H03M1/02 , H03M1/468 , H03M1/804
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译：一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。一组二进制加权电容器存储模拟输入。开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。分析比较结果以确定模拟输入的最接近的数字值。在DAC模式下，基于输入数字值切换阵列电容器。开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。可重新配置的比较器级的增益适用于ADC和DAC模式。

3. 发明申请

US20100164761A1 DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC 有权
标题翻译：双使用比较器/运算放大器，用作两个ADC，DAC和DAC
公开(公告)号：US20100164761A1
公开(公告)日：2010-07-01
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/02 , H03M1/12 , H03M3/02
CPC分类号： H03M1/02 , H03M1/468 , H03M1/804
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译：一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。一组二进制加权电容器存储模拟输入。开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。分析比较结果以确定模拟输入的最接近的数字值。在DAC模式下，基于输入数字值切换阵列电容器。开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。可重新配置的比较器级的增益适用于ADC和DAC模式。

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