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1. 发明申请

US20070260962A1 Methods and apparatus for a memory device with self-healing reference bits 有权
标题翻译：具有自修复参考位的存储器件的方法和装置
公开(公告)号：US20070260962A1
公开(公告)日：2007-11-08
申请号：US11416850
申请日：2006-05-02
申请人： Loren Wise , Thomas Andre , Mark Durlam , Eric Salter
发明人： Loren Wise , Thomas Andre , Mark Durlam , Eric Salter
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1008 , G11C11/16
摘要： A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the reference bits (104) is toggled to a different state if an error count is greater than a predetermined threshold. If the set of errors remains unchanged when subsequently read, the reference bit (104) is toggled back to its original state.
摘要翻译：诸如MRAM设备的存储器件包括与一组阵列位（102）相关联的自修复参考位（104）。存储器执行错误检测步骤（例如，使用纠错编码（ECC）算法）来检测数据位内的一组错误的存在，其中一个参考位（104）被切换到不同的状态，如果错误计数大于预定阈值，如果随后读取的错误集合保持不变，则将参考位（104）切换回其初始状态。

2. 发明申请

US20070077664A1 Magnetic tunnel junction temperature sensors and methods 失效
标题翻译：磁隧道结温度传感器及方法
公开(公告)号：US20070077664A1
公开(公告)日：2007-04-05
申请号：US11239884
申请日：2005-09-30
申请人： Young Chung , Robert Baird , Mark Durlam
发明人： Young Chung , Robert Baird , Mark Durlam
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L27/228 , G01K7/36 , Y10T428/1114
摘要： Techniques of sensing a temperature of a heat source disposed in a substrate of an integrated circuit are provided. According to one exemplary method, a Magnetic Tunnel Junction (“MTJ”) temperature sensor is provided over the heat source. The MTJ temperature sensor comprises an MTJ core configured to output a current during operation thereof. The value of the current varies based on a resistance value of the particular MTJ core. The resistance value of the MTJ core varies as a function of the temperature of the heat source. A value of the current of the MTJ core can then be associated with a corresponding temperature of the heat source.
摘要翻译：提供了感测设置在集成电路的基板中的热源的温度的技术。根据一个示例性方法，在热源上提供磁隧道结（“MTJ”）温度传感器。 MTJ温度传感器包括被配置为在其操作期间输出电流的MTJ内核。电流值根据特定MTJ磁芯的电阻值而变化。 MTJ芯的电阻值随着热源的温度而变化。然后，MTJ芯的电流的值可以与热源的相应温度相关联。

3. 发明申请

US20060170068A1 MAGNETOELECTRONIC DEVICES UTILIZING PROTECTIVE CAPPING LAYERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：使用保护层的磁电装置及其制造方法
公开(公告)号：US20060170068A1
公开(公告)日：2006-08-03
申请号：US11048015
申请日：2005-01-31
申请人： J. Ren , Brian Butcher , Mark Durlam , Gregory Grynkewich
发明人： J. Ren , Brian Butcher , Mark Durlam , Gregory Grynkewich
IPC分类号： H01L43/00 , H01L29/82
CPC分类号： H01L43/12 , H01L27/228
摘要： Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.
摘要翻译：提供了磁电子器件结构及其制造方法。一种方法包括形成第一和第二导体。第一导体电耦合到互连叠层。沉积在第一导体和第二导体上的第一绝缘层。蚀刻通孔以基本上暴露第一导体。通过无孔沉积在通孔内沉积保护性覆盖层并电耦合到第一导体。磁通存储元件层形成在通孔内并覆盖第二绝缘层和第二导体。

4. 发明申请

US20050152183A1 MRAM architecture with electrically isolated read and write circuitry 有权
公开(公告)号：US20050152183A1
公开(公告)日：2005-07-14
申请号：US11076523
申请日：2005-03-09
申请人： Joseph Nahas , Thomas Andre , Chitra Subramanian , Bradley Garni , Mark Durlam
发明人： Joseph Nahas , Thomas Andre , Chitra Subramanian , Bradley Garni , Mark Durlam
IPC分类号： G11C11/16 , G11C11/14
CPC分类号： G11C11/16
摘要： A magnetoresistive random access memory (MRAM) has separate read and write paths. This reduces the peripheral circuitry by not requiring switching between read and write functions on a particular line. By having the paths dedicated to either read signals or write signals, the voltage levels can be optimized for these functions. The select transistors, which are part of only the read function, may be of the low-voltage type because they do not have to receive the relatively higher voltages of the write circuitry. Similarly, the write voltages do not have to be degraded to accommodate the lower-voltage type transistors. The size of the overall memory is kept efficiently small while improving performance. The memory cells are grouped so that adjacent to groups are coupled to a common global bit line which reduces the space required for providing the capacitance-reducing group approach to memory cell selection.

5. 发明申请

US20050130374A1 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
公开(公告)号：US20050130374A1
公开(公告)日：2005-06-16
申请号：US11050191
申请日：2005-02-02
申请人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Kelly Kyler , Charles Synder , Kenneth Smith , Clarence Tracy , Richard Williams
发明人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Kelly Kyler , Charles Synder , Kenneth Smith , Clarence Tracy , Richard Williams
IPC分类号： G11C11/15 , H01L21/8246 , H01L43/12 , H01L21/336
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

6. 发明授权

US06174737B1 Magnetic random access memory and fabricating method thereof 有权
标题翻译：磁性随机存取存储器及其制造方法
公开(公告)号：US06174737B1
公开(公告)日：2001-01-16
申请号：US09339460
申请日：1999-06-24
申请人： Mark Durlam , Gloria Kerszykowski , Jon Slaughter , Theodore Zhu , Eugene Chen , Saied N. Tehrani , Kelly W. Kyler
发明人： Mark Durlam , Gloria Kerszykowski , Jon Slaughter , Theodore Zhu , Eugene Chen , Saied N. Tehrani , Kelly W. Kyler
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , H01L27/224
摘要： An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).
摘要翻译：提供了一种具有磁存储器元件和用于控制磁存储元件的电路的改进和新颖的MRAM器件。电路，例如具有栅极（17a），漏极（18）和源极（16a）的晶体管（12a）集成在衬底（11）上并且耦合到电路上的磁存储元件（43），通过插头导体（19a）和导线（45）。首先在CMOS工艺之下制造电路，然后制造磁存储元件（43,44）。数字线（29）和位线（48）分别放置在磁存储元件（43）的下面和顶部，并且能够访问磁存储元件（43）。这些线被除了面向磁性存储元件（43）的高磁导率层（31,56,58）包围，磁性层屏蔽并将磁场聚焦到磁性存储元件（43）。

7. 发明申请

US20070076330A1 Magnetic tunnel junction temperature sensors 失效
标题翻译：磁隧道结温度传感器
公开(公告)号：US20070076330A1
公开(公告)日：2007-04-05
申请号：US11240514
申请日：2005-09-30
申请人： Young Chung , Robert Baird , Mark Durlam
发明人： Young Chung , Robert Baird , Mark Durlam
IPC分类号： G11B5/33
CPC分类号： G11C11/16 , G01K7/01 , G11C29/50 , G11C29/50008 , G11C2029/5002
摘要： An integrated circuit device is provided which includes a heat source disposed in a substrate, and a Magnetic Tunnel Junction (“MTJ”) temperature sensor disposed over the heat source.
摘要翻译：提供一种集成电路装置，其包括设置在基板中的热源和设置在热源上方的磁隧道结（“MTJ”）温度传感器。

8. 发明申请

US20070045759A1 Passive elements in MRAM embedded integrated circuits 有权
公开(公告)号：US20070045759A1
公开(公告)日：2007-03-01
申请号：US11217146
申请日：2005-08-31
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： H01L43/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

9. 发明申请

US20070002609A1 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US20070002609A1
公开(公告)日：2007-01-04
申请号：US11170874
申请日：2005-06-30
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： G11C11/14
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

10. 发明申请

US20050164413A1 METHOD FOR FABRICATING A FLUX CONCENTRATING SYSTEM FOR USE IN A MAGNETOELECTRONICS DEVICE 有权
标题翻译：一种用于磁电子设备的通量浓度系统的制造方法
公开(公告)号：US20050164413A1
公开(公告)日：2005-07-28
申请号：US10324716
申请日：2002-12-19
申请人： Thomas Meixner , Gregory Grynkewich , Jaynal Molla , J. Ren , Richard Williams , Brian Butcher , Mark Durlam
发明人： Thomas Meixner , Gregory Grynkewich , Jaynal Molla , J. Ren , Richard Williams , Brian Butcher , Mark Durlam
IPC分类号： G11C11/16 , H01L21/8246 , H01L21/00 , H01L21/20
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
摘要翻译：提供了一种用于制造用于磁电装置的通量集中系统（62）的方法。该方法包括以下步骤：提供在衬底（12）中形成的位线（10），并形成覆盖位线（10）和衬底（12）的第一材料层（24）。进行蚀刻以在第一材料层（24）中形成沟槽（58），并且在沟槽（52）中沉积包层（56）。缓冲材料层（58）形成在覆层（56）上，缓冲材料层（58）的一部分和包覆层（56）的一部分被去除。

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