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1. 发明授权

US07242383B2 Portable microdisplay system 有权
标题翻译：便携式微显示系统
公开(公告)号：US07242383B2
公开(公告)日：2007-07-10
申请号：US09309155
申请日：1999-05-10
申请人： Matthew Zavracky , Jeffrey Jacobsen , Frederick P. Herrmann , Wen-Foo Chern , Hiap L. Ong , John C. C. Fan , Bor-Yeu Tsaur , Alan Richard , Ronald P. Gale , Jason Lo , Stephen A. Pombo , Rodney Bumgardner
发明人： Matthew Zavracky , Jeffrey Jacobsen , Frederick P. Herrmann , Wen-Foo Chern , Hiap L. Ong , John C. C. Fan , Bor-Yeu Tsaur , Alan Richard , Ronald P. Gale , Jason Lo , Stephen A. Pombo , Rodney Bumgardner
IPC分类号： G09G3/36
CPC分类号： H04N9/30 , G06F1/1616 , G06F1/1626 , G06F1/163 , G06F1/1632 , G06F1/1637 , G06F1/1656 , G06F1/1662 , G06F1/1686 , G06F1/1698 , G09G3/3406 , G09G3/3413 , G09G3/3659 , G09G2310/0235 , G09G2310/024 , G09G2310/08 , G09G2320/041 , G09G2320/0633 , G09G2320/064 , G09G2330/021
摘要： An active matrix color crystal display has an active matrix circuit, a counterelectrode panel and an interposed layer of liquid crystal. The active matrix display is located in a portable microdisplay system that has a display computer that generates images to be displayed on the liquid crystal display and connected to the active matrix liquid crystal display. A data link transmits data at a rate of speed of greater than 200 Mbytes per second in series for at least a portion between the display computer and the active matrix liquid crystal display. In a preferred embodiment, the display system has a randomizing device that alternates the amplifier through which an analog video signal passes.
摘要翻译：有源矩阵彩色晶体显示器具有有源矩阵电路，反电极面板和插入的液晶层。有源矩阵显示器位于具有显示计算机的便携式微型显示系统中，显示计算机产生要显示在液晶显示器上并连接到有源矩阵液晶显示器的图像。数据链路以显示计算机和有源矩阵液晶显示器之间的至少一部分串联发送速度大于每秒200兆字节的速率的数据。在优选实施例中，显示系统具有随机化装置，其交替模拟视频信号通过的放大器。

2. 发明授权

US06232937B1 Low power active display system 失效
标题翻译：低功率主动显示系统
公开(公告)号：US06232937B1
公开(公告)日：2001-05-15
申请号：US08884485
申请日：1997-06-27
申请人： Jeffrey Jacobsen , John C. C. Fan , Stephen A. Pombo , Matthew Zavracky , Rodney Bumgardner , Alan Richard , Wen-Foo Chern
发明人： Jeffrey Jacobsen , John C. C. Fan , Stephen A. Pombo , Matthew Zavracky , Rodney Bumgardner , Alan Richard , Wen-Foo Chern
IPC分类号： G09G336
CPC分类号： H04N7/142 , G02B25/002 , G09G3/001 , G09G3/3406 , G09G3/3614 , G09G3/3648 , G09G3/3659 , G09G3/3688 , G09G5/18 , G09G5/39 , G09G5/391 , G09G2300/0408 , G09G2310/0235 , G09G2310/0283 , G09G2310/063 , G09G2320/0209 , G09G2320/041 , G09G2330/021 , G09G2340/0407 , G09G2340/0492 , H04M1/0202 , H04M1/021 , H04M1/0214 , H04M1/0247 , H04M1/0254 , H04M1/0264 , H04M2250/20 , H04N9/3141
摘要： The invention relates to a microdisplay system that utilizes a small high resolution active matrix liquid crystal display with an illumination system and a magnifying optical system to provide a hand held communication display device. The system has an alternating common voltage which allows reduced power consumption. In addition an internal heating system in the display allows the system to be used at low temperatures. The system can employ an LED illumination system and cellular communication or processor circuits within a compact housing to provide communication devices such as pagers, telephones, televisions, and hand held computer or card reader devices with a compact high resolution data and/or video display.
摘要翻译：本发明涉及利用具有照明系统的小型高分辨率有源矩阵液晶显示器和放大光学系统来提供手持式通信显示装置的微型显示系统。该系统具有交替的公共电压，可以降低功耗。此外，显示器中的内部加热系统允许系统在低温下使用。该系统可以使用紧凑壳体内的LED照明系统和蜂窝通信或处理器电路来提供具有紧凑的高分辨率数据和/或视频显示器的通信设备，例如寻呼机，电话机，电视机，以及手持计算机或读卡器设备。

3. 发明授权

US6124625A Chip decoupling capacitor 失效
标题翻译：芯片去耦电容
公开(公告)号：US6124625A
公开(公告)日：2000-09-26
申请号：US916184
申请日：1997-08-21
申请人： Wen-Foo Chern , Ward D. Parkinson , Thomas M. Trent , Kevin G. Duesman
发明人： Wen-Foo Chern , Ward D. Parkinson , Thomas M. Trent , Kevin G. Duesman
IPC分类号： H01L27/02 , H01L27/08 , H05K1/02 , H01L29/00 , H01L27/108 , H01L29/93
CPC分类号： H01L27/0805 , H01L27/0214 , H05K1/0231
摘要： An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.
摘要翻译：一个广泛的N沟道晶体管形成的电容网络，其一个节点直接连接到VCC电源总线，另一个节点直接连接VSS电源总线，在整个硅芯片（存储器和逻辑芯片）上可用的所有开放空间中实现，特别是那些直接在金属电源总线下面的那些，以实现片上电源总线去耦电容器，电容值超过0.001μF。

4. 发明授权

US5530668A Ferroelectric memory sensing scheme using bit lines precharged to a logic one voltage 失效
标题翻译：铁电存储器感测方案使用预充电到逻辑1电压的位线
公开(公告)号：US5530668A
公开(公告)日：1996-06-25
申请号：US420752
申请日：1995-04-12
申请人： Wen-Foo Chern , Dennis Wilson
发明人： Wen-Foo Chern , Dennis Wilson
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C11/22
摘要： In a ferroelectric memory cell having a plate line, a word line and a bit line coupled to a sense amplifier, a sensing method includes the steps of precharging the bit line to a logic one voltage, setting the word and plate lines to an initial logic zero voltage, stepping the word line from the initial logic zero voltage to the logic one voltage, stepping the plate line from the initial logic zero voltage to the logic one voltage, activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage, and returning the word and plate lines to the initial logic zero voltage.
摘要翻译：在具有板线，字线和耦合到读出放大器的位线的铁电存储单元中，感测方法包括以下步骤：将位线预充电到逻辑1电压，将字线和板线设置为初始逻辑零电压，将字线从初始逻辑零电压步进到逻辑1电压，将板极线从初始逻辑零电压步进到逻辑1电压，激活读出放大器，将位线上产生的电压解析为满逻辑电压，而字线和平板线处于逻辑1电压，并将字线和平板线返回到初始逻辑零电压。

5. 发明授权

US5381364A Ferroelectric-based RAM sensing scheme including bit-line capacitance isolation 失效
标题翻译：基于铁电的RAM感测方案，包括位线电容隔离
公开(公告)号：US5381364A
公开(公告)日：1995-01-10
申请号：US83883
申请日：1993-06-24
申请人： Wen-Foo Chern , Brett Meadows
发明人： Wen-Foo Chern , Brett Meadows
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： G11C11/22
摘要： A ferroelectric memory includes a bit line for developing a signal coupled to a ferroelectric memory cell. An integrated load capacitor and sense amplifier are also coupled to the bit line. An isolation circuit is included for selectively electrically isolating the bit line load capacitor from the sense amplifier and ferroelectric memory cell during the active operation of the sense amplifier. The isolation circuit is compatible with both non-volatile ferroelectric and volatile dynamic memory operation.
摘要翻译：铁电存储器包括用于显影耦合到铁电存储器单元的信号的位线。集成的负载电容器和读出放大器也耦合到位线。包括隔离电路，用于在感测放大器的有效操作期间选择性地将位线负载电容器与读出放大器和铁电存储器单元电隔离。隔离电路兼容非易失性铁电和易失性动态存储器操作。

6. 发明授权

US5266821A Chip decoupling capacitor 失效
标题翻译：芯片去耦电容
公开(公告)号：US5266821A
公开(公告)日：1993-11-30
申请号：US970528
申请日：1992-11-02
申请人： Wen-Foo Chern , Ward D. Parkinson , Thomas M. Trent , Kevin G. Duesman
发明人： Wen-Foo Chern , Ward D. Parkinson , Thomas M. Trent , Kevin G. Duesman
IPC分类号： H01L27/02 , H01L27/08 , H05K1/02
CPC分类号： H01L27/0214 , H01L27/0805 , H05K1/0231
摘要： An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.
摘要翻译：广泛的N沟道晶体管形成的电容网络，一个节点直接连接到Vcc电源总线，另一个节点直接连接Vss电源总线，在整个硅芯片（存储器和逻辑芯片）上可用的所有开放空间实现，特别是那些直接在金属电源总线下面的那些，以实现片上电源总线去耦电容器，电容值超过0.001μF。

7. 发明授权

US5126590A High efficiency charge pump 失效
标题翻译：高效电荷泵
公开(公告)号：US5126590A
公开(公告)日：1992-06-30
申请号：US716697
申请日：1991-06-17
申请人： Wen-Foo Chern
发明人： Wen-Foo Chern
IPC分类号： G05F3/20 , H02M3/07
CPC分类号： H02M3/07 , G05F3/205
摘要： A high efficiency charge pump includes first and second charging transistors for delivering current to a substrate or well and first and second capacitors respectively coupled to the first and second charging transistors. A control circuit coupled to the first and second charging transistors discharges the first capacitor through the first charging transistor and precharges the second capacitor during a first half-cycle of a ring oscillator output signal. The control circuit discharges the second capacitor through the second charging transistor and precharges the first capacitor during a second half-cycle of the ring oscillator output signal. The control circuit also includes first and second symmetrical halves respectively coupled to third and fourth capacitors. The first, second, third, and fourth capacitors are energized by a four-phase clock signal.
摘要翻译：高效率电荷泵包括用于将电流传送到衬底或阱的第一和第二充电晶体管以及分别耦合到第一和第二充电晶体管的第一和第二电容器。耦合到第一和第二充电晶体管的控制电路通过第一充电晶体管放电第一电容器，并且在环形振荡器输出信号的第一半周期期间对第二电容器进行预充电。控制电路通过第二充电晶体管放电第二电容器，并且在环形振荡器输出信号的第二个半周期期间对第一电容器进行预充电。控制电路还包括分别耦合到第三和第四电容器的第一和第二对称半部。第一，第二，第三和第四电容器被四相时钟信号激励。

8. 发明授权

US5118968A Special mode activation circuit for selectively activating a special mode circuit of a semiconductor integrated circuit device 失效
标题翻译：用于选择性地激活半导体集成电路器件的特殊模式电路的特殊模式激活电路
公开(公告)号：US5118968A
公开(公告)日：1992-06-02
申请号：US581587
申请日：1990-09-12
申请人： Kurt P. Douglas , Wen-Foo Chern , Vijaya B. Wickremarachchi
发明人： Kurt P. Douglas , Wen-Foo Chern , Vijaya B. Wickremarachchi
IPC分类号： H03K5/1534 , H03K17/30
CPC分类号： H03K5/1534 , H03K17/302
摘要： A special mode activation circuit is disclosed for activating a special mode circuit within a semiconductor integrated circuit when the voltage of an input signal at an input terminal of the integrated circuit reaches a special high voltage level that is substantially above a low voltage level range of signals normally associated with binary logic levels. The special mode activation circuit comprises a voltage reduction subcircuit, a voltage detection subcircuit, and an active pullup subcircuit. The voltage reduction subcircuit reduces the voltage of the input signal to generate a reduced voltage input signal. The voltage detection subcircuit is responsive to the reduced voltage signal to prevent activation of the special mode circuit when the reduced voltage input signal is less than a preset threshold value and to activate the special mode circuit when reduced voltage input signal exceeds the preset threshold value. The active pullup subcircuit maintains the voltage of the reduced voltage input signal above a minimum voltage to (1) prevent leakage current through the voltage reduction subcircuit, (2) reduce the voltage change required in the reduced voltage input signal to activate the special mode circuit, and (3) reduce the possibility of induced latchup.
摘要翻译：公开了一种特殊模式激活电路，用于在集成电路的输入端处的输入信号的电压达到特别的高电压电平时启动半导体集成电路内的特殊模式电路，该高电压电平基本上高于信号的低电压电平范围通常与二进制逻辑电平相关。特殊模式激活电路包括降压子电路，电压检测子电路和有源上拉子电路。降压分支电路降低输入信号的电压，以产生降低的电压输入信号。当降低的电压输入信号小于预设的阈值时，电压检测子电路响应于降低的电压信号以防止特殊模式电路的激活，并且当减小的电压输入信号超过预设的阈值时激活特殊模式电路。有源上拉分支电路将降低电压输入信号的电压保持在最小电压以上，以（1）防止漏电流通过降压子电路，（2）降低降压输入信号所需的电压变化，激活特殊模式电路，（3）减少诱发闭锁的可能性。

9. 发明授权

US5039877A Low current substrate bias generator 失效
标题翻译：低电流衬底偏置发生器
公开(公告)号：US5039877A
公开(公告)日：1991-08-13
申请号：US575151
申请日：1990-08-30
申请人： Wen-Foo Chern
发明人： Wen-Foo Chern
IPC分类号： G11C11/413 , G11C11/408 , H01L21/822 , H01L27/04 , H02M3/07 , H03K19/094 , H03L1/00
CPC分类号： H03L1/00
摘要： A low current substrate bias generator for regulating the voltage of a substrate layer of an integrated circuit includes a sense circuit having an input for sensing the voltage of the substrate and an output that is coupled to an inverter for providing a control signal. The control signal controls a charge pump that is coupled to the substrate layer or well that is desired to be regulated. The sense circuit includes a load element and a level shifting circuit having a predetermined standing current requirement that flows directly into the substrate. The current requirement of the bias generator is reduced by increasing the value of the load element and a reasonable delay time is maintained by coupling a capacitor across the level shifting circuit. Since the voltage across the capacitor cannot be changed instantaneously, changes in the substrate voltage are directly coupled from the input to the output of the sense circuit, triggering the charge pump. Regulation of the substrate voltage level proceeds with no corresponding increase in delay time.
摘要翻译：用于调节集成电路的衬底层的电压的低电流衬底偏置发生器包括具有用于感测衬底的电压的输入的感测电路和耦合到用于提供控制信号的逆变器的输出。控制信号控制耦合到期望调节的衬底层或阱的电荷泵。感测电路包括负载元件和电平移动电路，其具有直接流入基板的预定的直流电流要求。通过增加负载元件的值来减少偏置发生器的电流要求，并且通过将电容器跨越电平移动电路来维持合理的延迟时间。由于电容器两端的电压不能立即改变，所以基板电压的变化从输入到感测电路的输出直接耦合，触发电荷泵。衬底电压电平的调节在延迟时间没有相应的增加的情况下进行。

10. 发明授权

US5023465A High efficiency charge pump circuit 失效
标题翻译：高效率电荷泵电路
公开(公告)号：US5023465A
公开(公告)日：1991-06-11
申请号：US498772
申请日：1990-03-26
申请人： Kurt P. Douglas , Wen-Foo Chern
发明人： Kurt P. Douglas , Wen-Foo Chern
IPC分类号： G05F3/20 , G11C5/14 , G11C11/4074 , H02M3/07
CPC分类号： G11C11/4074 , G05F3/205 , G11C5/145 , H02M3/07
摘要： An integrated circuit device includes a charge pump to provide current at a potential which is greater than a supply potential. A potential maintenance circuit gates on when the potential at the output of the charge pump circuit drops to a level which is below V.sub.CC. The potential maintenance circuit permits the charge pump can be bypassed or designed to provide a minimum current output. An overvoltage shutoff circuit permits the charge pump to be effectively bypassed when supply voltage is sufficiently high to make bypass desireable.
摘要翻译：集成电路器件包括电荷泵，以提供大于电源电位的电位。当电荷泵电路的输出端的电位下降到低于VCC的电平时，潜在的维护电路将导通。潜在维护电路允许电荷泵旁路或设计成提供最小电流输出。过电压关断电路允许当电源电压足够高以使旁路需要时电荷泵被有效地旁路。

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