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    • 3. 发明授权
      US5302870A Apparatus for providing multi-level potentials at a sense node 失效
    • Apparatus for providing multi-level potentials at a sense node
    • 用于在感测节点处提供多电平电位的装置
    • US5302870A
    • 1994-04-12
    • US001429
    • 1993-01-06
    • Wen-Foo Chern
    • Wen-Foo Chern
    • G11C7/06 , G11C11/4091 , H03F3/45 , H03K19/02
    • G11C11/4091 , G11C7/06
    • A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage. The initial momentary discharge of the sense node to the first potential allows a sense amplifier to behave like a conventional sense amplifier during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground. Decreasing the second potential to a third potential at the initiation of the precharge cycle effects a decrease in the equilibrate potential of the digit lines, thereby increasing the "high logic window" as reflected in an increase in cell margin and a decrease in soft error rate (SER).
    • 一种多电平电位产生电路，通过首先使节点接地到等于参考电位的第一电位，将感测节点带到三个电位，然后使节点浮动到等于参考电位的基本稳定的第二电位加上等于参考电位的阈值电压 通过漏电流泵送的电气装置。 然后将第二电位降低到大于或等于第一电位的第三电势。 这里描述的电压感测通常用于在DRAM周期的有效部分期间以及在DRAM周期的预充电部分的启动期间偏置动态随机存取存储器（DRAM）器件中的数字线。 第二电位减小了存储单元的电流泄漏，而不利用具有高阈值电压的电气装置。 感测节点到初始电位的初始瞬时放电允许读出放大器在初始感测期间像传统的读出放大器一样，从而允许最小数字/数字*感测电位近似接近。 在预充电循环开始时，将第二电势降低到第三电位，使得数字线的平衡电位降低，从而增加“高逻辑窗”，反映在单元余量的增加和软错误率的降低 （SER）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5132575A Method for providing multi-level potentials at a sense node 失效
    • Method for providing multi-level potentials at a sense node
    • 在感测节点提供多电平电位的方法
    • US5132575A
    • 1992-07-21
    • US749247
    • 1991-08-23
    • Wen-Foo Chern
    • Wen-Foo Chern
    • G11C7/06 , G11C11/4091
    • G11C11/4091 , G11C7/06
    • Voltage sensing brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage. The initial momentary discharge of the sense node to the first potential allows a sense amplifier to behave like a conventional sense amplifier during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground. Decreasing the second potential to a third potential at the initiation of the precharge cycle effects a decrease in the equilibrate potential of the digit lines, thereby increasing the "high logic window" as reflected in an increase in cell margin and a decrease in soft error rate (SER).
    • 电压感测通过首先将节点接地到等于参考电位的第一电位，然后将节点漂浮到等于参考电位的基本稳定的第二电位加上电气设备的阈值电压，从而将感测节点带到三个电位，通过该阈值电压泄漏 电流被泵送。 然后将第二电位降低到大于或等于第一电位的第三电势。 这里描述的电压感测通常用于在DRAM周期的有效部分期间以及在DRAM周期的预充电部分的启动期间偏置动态随机存取存储器（DRAM）器件中的数字线。 第二电位减小了存储单元的电流泄漏，而不利用具有高阈值电压的电气装置。 感测节点到初始电位的初始瞬时放电允许读出放大器在初始感测期间像传统的读出放大器一样，从而允许最小数字/数字*感测电位近似接近。 在预充电循环开始时，将第二电势降低到第三电位，使得数字线的平衡电位降低，从而增加“高逻辑窗”，反映在单元余量的增加和软错误率的降低 （SER）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5038325A High efficiency charge pump circuit 失效
    • High efficiency charge pump circuit
    • 高效率电荷泵电路
    • US5038325A
    • 1991-08-06
    • US487773
    • 1990-03-26
    • Kurt P. Douglas , Wen-Foo Chern
    • Kurt P. Douglas , Wen-Foo Chern
    • G11C5/14 , G11C11/4074 , H02M3/07
    • H02M3/07 , G11C11/4074 , G11C5/145
    • An integrated circuit includes a charge pump to provide current at a potential which is greater than a supply potential. An oscillator provides an output to a pair of capacitors. Each capacitor is bypassed respectively by one of a pair of clamp circuits. An output transistor is gated by one of the clamp circuits to maintain a continuous output at an elevated potential, while reducing power loss caused by impedances within the charge pump circuit. By using the charge pump as a source of elevated potential, the circuit layout of the DRAM array is simplified and the potential boosting circuitry can be locataed outside of the array, on the periphery of the integrated circuit. When used with an integrated circuit device, such as a DRAM, the current from the charge pump may be supplied to nodes on isolation devices and nodes on word lines, thereby improving the performance of the DRAM without substantially changing the circuit configuration of the DRAM array.
    • 集成电路包括电荷泵，以提供大于电源电位的电位。 振荡器为一对电容器提供输出。 每个电容器分别由一对钳位电路中的一个旁路。 输出晶体管由钳位电路之一选通，以保持连续输出处于升高的电位，同时减少由电荷泵电路内的阻抗引起的功率损耗。 通过使用电荷泵作为升高的电位源，DRAM阵列的电路布局被简化，并且电位升压电路可以位于集成电路外围的阵列之外。 当与诸如DRAM的集成电路器件一起使用时，来自电荷泵的电流可以被提供给字线上的隔离器件和节点上的节点，从而在不改变DRAM阵列的电路配置的情况下提高DRAM的性能 。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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