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1. 发明授权

US08390075B2 Semiconductor memory devices and methods of fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08390075B2
公开(公告)日：2013-03-05
申请号：US12588717
申请日：2009-10-26
申请人： Weon-ho Park
发明人： Weon-ho Park
IPC分类号： H01L27/115
CPC分类号： H01L27/112 , H01L27/11521 , H01L27/11526
摘要： Semiconductor memory devices and methods of fabricating the semiconductor memory devices are provided, the semiconductor memory devices may include a one-time-programmable (OTP) cell and an electrically erasable programmable read-only memory (EEPROM). The OTP cell includes a memory transistor and a program transistor. The program transistor may include a fuse electrode and may be spaced apart from the memory transistor. The EEPROM cell includes a memory transistor including a first gate and a selection transistor including a second gate. The OTP cell includes a first high-density impurity region which overlaps with the fuse electrode.
摘要翻译：提供半导体存储器件和制造半导体存储器件的方法，半导体存储器件可以包括一次可编程（OTP）单元和电可擦除可编程只读存储器（EEPROM）。 OTP单元包括存储晶体管和程序晶体管。程序晶体管可以包括熔丝电极并且可以与存储晶体管间隔开。 EEPROM单元包括存储晶体管，其包括第一栅极和包括第二栅极的选择晶体管。 OTP单元包括与熔丝电极重叠的第一高密度杂质区。

2. 发明授权

US07408219B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07408219B2
公开(公告)日：2008-08-05
申请号：US11099658
申请日：2005-04-06
申请人： Tea-kwang Yu , Weon-ho Park , Kyoung-hwan Kim , Kwang-tae Kim
发明人： Tea-kwang Yu , Weon-ho Park , Kyoung-hwan Kim , Kwang-tae Kim
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer.
摘要翻译：在非易失性半导体存储器件及其制造方法中，非易失性半导体存储器件包括半导体衬底中的单元掺杂区域和源极/漏极区域，该单元掺杂区域被掺杂为第一导电类型，沟道区域设置在半导体衬底中的源极/漏极区之间，形成在电池掺杂区的上部的预定区域中的第一导电类型的隧道掺杂区，掺杂浓度高于在隧道掺杂区域上形成在半导体衬底的表面上的隧道绝缘层，围绕隧道绝缘层并覆盖沟道区域的栅极绝缘层和暴露在隧道掺杂区域外的电池掺杂区域，以及栅电极覆盖隧道绝缘层和栅极绝缘层。

3. 发明申请

US20080142869A1 Non-volatile memory device and method of forming the same 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20080142869A1
公开(公告)日：2008-06-19
申请号：US11987294
申请日：2007-11-29
申请人： Kong-Sam Jang , Jeong-uk Han , Yong-tae Kim , Weon-ho Park
发明人： Kong-Sam Jang , Jeong-uk Han , Yong-tae Kim , Weon-ho Park
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42328
摘要： Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided on the semiconductor substrate so as to cover a first end of the conductive pattern. The first end may include an upward tapering, first protrusion. A select gate structure may be provided on the semiconductor substrate so as to cover the second end of the conductive pattern. The second end may include an upward tapering, second protrusion. The coverage of the first protrusion by the memory gate structure may be greater than the coverage of the second protrusion by the select gate structure.
摘要翻译：示例性实施例涉及非易失性存储器件及其形成方法。根据示例性实施例的非易失性存储器件可以包括设置在半导体衬底上的导电图案。隧道绝缘体可以设置在导电图案上。可以在半导体衬底上提供存储栅结构，以便覆盖导电图案的第一端。第一端可包括向上逐渐变细的第一突起。可以在半导体衬底上设置选择栅极结构，以覆盖导电图案的第二端。第二端可以包括向上渐缩的第二突起。通过存储器栅极结构的第一突起的覆盖可以大于通过选择栅极结构的第二突起的覆盖。

4. 发明申请

US20080054345A1 Electrically erasable and programmable read only memory device and method of manufacturing the same 失效
标题翻译：电可擦除和可编程只读存储器件及其制造方法
公开(公告)号：US20080054345A1
公开(公告)日：2008-03-06
申请号：US11891605
申请日：2007-08-10
申请人： Weon-Ho Park , Jeong-Uk Han , Yong-Tae Kim
发明人： Weon-Ho Park , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.
摘要翻译：提供电可擦除可编程只读存储器（EEPROM）器件和制造EEPROM器件的方法。在形成在基板上的隧道绝缘层上形成具有相同结构的第一和第二栅极结构，使得第一和第二栅极结构彼此间隔开。在位于第一和第二栅极结构之间的衬底的一部分处形成公共源区。第一和第二漏极区分别形成在与第一和第二栅极结构相邻的衬底的第一和第二部分处。因此，制造EEPROM器件，其包括具有相同结构的第一和第二晶体管，并且可以根据施加的信号交替地用作存储晶体管和选择晶体管。

5. 发明申请

US20070262373A1 Non-volatile memory integrated circuit device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器集成电路器件及其制造方法
公开(公告)号：US20070262373A1
公开(公告)日：2007-11-15
申请号：US11800650
申请日：2007-05-07
申请人： Weon-ho Park , Jeong-uk Han , Yong-tae Kim , Tea-kwang Yu , Kwang-tae Kim , Ji-hoon Park
发明人： Weon-ho Park , Jeong-uk Han , Yong-tae Kim , Tea-kwang Yu , Kwang-tae Kim , Ji-hoon Park
IPC分类号： H01L29/792
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324
摘要： A non-volatile memory integrated circuit device and a method of fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, a tunneling dielectric layer, a memory gate and a select gate, a floating junction region, a bit line junction region and a common source region, and a tunneling-prevention dielectric layer pattern. The tunneling dielectric layer is formed on the semiconductor substrate. The memory gate and a select gate are formed on the tunneling dielectric layer to be spaced apart from each other. The floating junction region is formed within the semiconductor substrate between the memory gate and the select gate, the bit line junction region is formed opposite the floating junction region with respect to the memory gate, and a common source region is formed opposite the floating junction region with respect to the select gate. The tunneling-prevention dielectric layer pattern is interposed between the semiconductor substrate and the tunneling dielectric layer, and is configured to overlap part of the memory gate.
摘要翻译：公开了一种非易失性存储器集成电路器件及其制造方法。非易失性存储器集成电路器件包括半导体衬底，隧道电介质层，存储栅极和选择栅极，浮置结区域，位线结区域和公共源极区域，以及防止隧道的电介质层图案。隧道介电层形成在半导体衬底上。存储器栅极和选择栅极形成在隧道电介质层上以彼此间隔开。在存储栅极和选择栅极之间的半导体衬底内形成浮点结区域，与存储栅极相对地形成位线接合区域，并且与浮置结区域相对形成公共源极区域相对于选择门。防止隧道的电介质层图案介于半导体衬底和隧穿电介质层之间，并被配置为与存储器栅极的一部分重叠。

6. 发明申请

US20060199334A1 EEPROM device and method of fabricating the same 失效
标题翻译： EEPROM装置及其制造方法
公开(公告)号：US20060199334A1
公开(公告)日：2006-09-07
申请号：US11418425
申请日：2006-05-04
申请人： Weon-Ho Park , Hyun-Khe Yoo
发明人： Weon-Ho Park , Hyun-Khe Yoo
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： A memory device comprises a semiconductor substrate of a first conductive type, a memory transistor, a select transistor, a floating junction region, a common source region, and a bit line junction region. The memory transistor positions on the semiconductor substrate and comprises a gate insulating film formed on the semiconductor substrate and a memory transistor gate formed on the gate insulating film. The gate insulating film includes a tunnel insulating film. The select transistor positions on the semiconductor substrate and is separated from the memory transistor gate. The select transistor comprises a gate insulating film formed on the semiconductor substrate and a select transistor gate formed on the gate insulating film. A floating junction region is formed of a second conductive type on the semiconductor substrate below the tunnel insulating film. The common source region of a second conductive type is formed on the semiconductor substrate adjacent to the memory transistor gate and separated from the floating junction region. A bit line junction region of a second conductive type is formed on the semiconductor substrate adjacent to the select transistor gate and is separated from the floating junction region, wherein the common source region includes a single junction region with a first doping concentration, and a depth of the common source region is shallower than a depth of the floating junction region and the bit line junction region.
摘要翻译：存储器件包括第一导电类型的半导体衬底，存储晶体管，选择晶体管，浮动结区域，公共源极区域和位线结区域。存储晶体管位于半导体衬底上并且包括形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的存储晶体管栅极。栅极绝缘膜包括隧道绝缘膜。选择晶体管位于半导体衬底上并与存储晶体管栅极分离。选择晶体管包括形成在半导体衬底上的栅极绝缘膜和形成在栅极绝缘膜上的选择晶体管栅极。在隧道绝缘膜下方的半导体衬底上，由第二导电类型形成浮接区。第二导电类型的公共源极区域形成在与存储晶体管栅极相邻并且与浮置结区域分离的半导体衬底上。第二导电类型的位线结区域形成在与选择晶体管栅极相邻的半导体衬底上，并与浮置结区域分离，其中公共源极区域包括具有第一掺杂浓度的单结区域和深度公共源极区域比浮置结区域和位线结区域的深度浅。

7. 发明申请

US20050117443A1 EEPROM cell and EEPROM device with high integration and low source resistance and method of manufacturing the same 失效
标题翻译： EEPROM单元和EEPROM器件具有高集成度和低源电阻及其制造方法
公开(公告)号：US20050117443A1
公开(公告)日：2005-06-02
申请号：US10997835
申请日：2004-11-24
申请人： Weon-ho Park , Byoung-ho Kim , Hyun-khe Yoo , Seung-beom Yoon , Sung-chul Park , Ju-ri Kim , Kwang-tae Kim , Jeong-wook Han
发明人： Weon-ho Park , Byoung-ho Kim , Hyun-khe Yoo , Seung-beom Yoon , Sung-chul Park , Ju-ri Kim , Kwang-tae Kim , Jeong-wook Han
IPC分类号： H01L27/115 , G11C8/02 , H01L21/8247
CPC分类号： H01L27/11524 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.
摘要翻译：提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的衬底上。具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。在第一区域中，第一漏极区域和第二浮动区域彼此分开地形成。在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度杂质区。

8. 发明授权

US06818509B2 Methods of fabricating electrically erasable programmable read-only memory (EEPROM) devices including multilayer sense and select transistor gates 失效
标题翻译：制造电可擦除可编程只读存储器（EEPROM）器件的方法包括多层感测和选择晶体管栅极
公开(公告)号：US06818509B2
公开(公告)日：2004-11-16
申请号：US10259090
申请日：2002-09-27
申请人： Weon-Ho Park , Min-Soo Cho , Jeung-Wook Han , Chil-Hee Chung
发明人： Weon-Ho Park , Min-Soo Cho , Jeung-Wook Han , Chil-Hee Chung
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/11524
摘要： EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer. The second conductive layer, the interlevel insulating layer and the first conductive layer then are patterned, to define a sense transistor gate on the tunnel insulating layer and on the gate insulating layer that comprises a first portion of the first conductive layer, a first portion of the interlevel insulating layer and a first portion of the second conductive layer, and to further define a select transistor gate on the gate insulating layer and spaced apart from the sense transistor gate, that comprises a second portion of the first conductive layer, a second portion of the interlevel insulating layer, and a second portion of the second conductive layer.
摘要翻译：可以通过形成栅极绝缘层和比集成电路衬底上的栅极绝缘层更薄的隧道绝缘层以及在隧道绝缘层下方的集成电路衬底中的第一掺杂区域栅极绝缘层。在隧道绝缘层和栅极绝缘层上依次形成第一导电层，层间绝缘层和第二导电层。然后对第二导电层，层间绝缘层和第一导电层进行构图，以在隧道绝缘层和栅极绝缘层上界定感测晶体管栅极，栅极绝缘层包括第一导电层的第一部分，第一部分所述层间绝缘层和所述第二导电层的第一部分，并且还在所述栅极绝缘层上限定选择晶体管栅极并且与所述感测晶体管栅极间隔开，所述选择晶体管栅极包括所述第一导电层的第二部分，第二部分以及第二导电层的第二部分。

9. 发明授权

US07852698B2 Voltage supply device and nonvolatile memory device having the same 有权
标题翻译：电压供应装置和具有该电压装置的非易失性存储装置
公开(公告)号：US07852698B2
公开(公告)日：2010-12-14
申请号：US12287184
申请日：2008-10-07
申请人： Min-Su Kim , Byoung-Ho Kim , Sung-Woo Park , Weon-Ho Park
发明人： Min-Su Kim , Byoung-Ho Kim , Sung-Woo Park , Weon-Ho Park
IPC分类号： G11C7/00
CPC分类号： H02M3/073 , G11C16/30 , H02M2001/0045
摘要： A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region.
摘要翻译：电压供给装置包括：电荷泵，被配置为升高电源电压并将升压的电源电压提供给输出线; 以及电压控制电路，被配置为将所述输出线的电压电平保持在目标电压电平; 其中所述电压控制电路包括直通元件，其包括设置在阱中的第一区域和第二区域，所述贯穿元件被配置为使用所述第一区域之间的到达功能来控制所述输出线路的电压电平和第二个地区。

10. 发明申请

US20100197109A1 METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US20100197109A1
公开(公告)日：2010-08-05
申请号：US12639035
申请日：2009-12-16
申请人： YONG-SIK JEONG , JEONG-UK HAN , WEON-HO PARK , BYUNG-SUP SHIM
发明人： YONG-SIK JEONG , JEONG-UK HAN , WEON-HO PARK , BYUNG-SUP SHIM
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76229
摘要： Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.
摘要翻译：提供了一种形成半导体器件的隔离结构的方法，该半导体器件能够最小化执行图案化处理的次数并具有各种深度的沟槽。该方法包括使用第一图案化工艺部分蚀刻半导体衬底以形成具有第一深度的第一沟槽和第二沟槽。半导体衬底具有第一至第三区域。第一沟槽形成在第一区域中，第二沟槽形成在第二区域中。使用第二图案化工艺部分地蚀刻半导体衬底，使得第三沟槽形成在第三区域中，并且第四沟槽形成在第二区域中。第四个沟槽从第二个沟槽的底部延伸。第三沟槽具有第二深度，第四沟槽具有第三深度。形成了填充第一至第四沟槽的隔离层。

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