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1. 发明授权

US6110775A Process for fabrication of a dram cell having a stacked capacitor 失效
标题翻译：具有堆叠电容器的电容器的制造方法
公开(公告)号：US6110775A
公开(公告)日：2000-08-29
申请号：US18181
申请日：1998-02-03
申请人： Toyokazu Fujii , Takatoshi Yasui
发明人： Toyokazu Fujii , Takatoshi Yasui
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/82 , H01L28/91
摘要： A DRAM cell transistor formed on a silicon substrate comprises a first BPSG film, a silicon oxide film as a supporting film laid thereover, a storage node including a contact portion filling a contact hole extended through the silicon oxide film and the first BPSG film, an oxidized silicon nitride film as a capacitor insulating film, and a plate electrode. There may be further provided a second BPSG film thereover. Even if the first BPSG film at a lower level is caused to reflow by a process for oxidizing the silicon nitride film for formation of the oxidized silicon nitride film as the capacitor insulating film or a process for ref lowing the second BPSG film, the silicon oxide film as the supporting film applies to the capacitor insulating film a stress against the deformation thereof and hence, the oxidized silicon nitride film free from wrinkle or cracks is provided as the capacitor insulating film. Thus, a semiconductor device free from wrinkle or cracks in the nitride film associated with thermal history and a process for fabrication of the same can be offered, even though the nitride film is laid over the insulating film having a reflowable property.
摘要翻译：形成在硅衬底上的DRAM单元晶体管包括第一BPSG膜，作为其上放置的支撑膜的氧化硅膜，存储节点，包括填充延伸穿过氧化硅膜的接触孔和第一BPSG膜的接触部分，氧化氮化硅膜作为电容器绝缘膜，和平板电极。此外可以进一步提供第二BPSG膜。即使通过用于氧化氮化硅膜以形成作为电容器绝缘膜的氧化的氮化硅膜的工艺或降低第二BPSG膜的工艺，使较低级别的第一BPSG膜回流，则氧化硅作为支撑膜的膜作为电容绝缘膜，适用于电容器绝缘膜对其变形的应力，因此，作为电容器绝缘膜，提供没有褶皱或裂纹的氧化的氮化硅膜。因此，即使将氮化膜覆盖在具有可回流性的绝缘膜上，也可以提供与热历史相关的氮化物膜中没有皱纹或裂纹的半导体器件及其制造方法。

2. 发明授权

US5652183A Method for fabricating semiconductor device containing excessive silicon in metal silicide film 失效
标题翻译：在金属硅化物膜中制造含有过量硅的半导体器件的方法
公开(公告)号：US5652183A
公开(公告)日：1997-07-29
申请号：US368604
申请日：1995-01-04
申请人： Toyokazu Fujii
发明人： Toyokazu Fujii
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76889
摘要： A method for fabricating a semiconductor device which includes a metal silicide film for electrically connecting a first silicon region containing a p-type impurity with a second silicon region containing an n-type impurity is disclosed. The method includes the step of depositing the metal silicide film so as to contain excessive silicon. Such excessive silicon is precipitated in silicide grain boundaries in the metal silicide film and thus makes a diffusion path of impurities along the silicide grain boundaries discontinuous.
摘要翻译：公开了一种制造半导体器件的方法，该半导体器件包括用于将含有p型杂质的第一硅区域与含有n型杂质的第二硅区域电连接的金属硅化物膜。该方法包括沉积金属硅化物膜以包含过多的硅的步骤。这种过量的硅在金属硅化物膜中的硅化物晶界析出，从而使杂质沿着硅化物晶界的不连续扩散路径。

3. 发明授权

US5314848A Method for manufacturing a semiconductor device using a heat treatment according to a temperature profile that prevents grain or particle precipitation during reflow 失效
标题翻译：根据温度分布的热处理制造半导体器件的方法，该温度分布防止在回流期间晶粒或颗粒沉淀
公开(公告)号：US5314848A
公开(公告)日：1994-05-24
申请号：US764846
申请日：1991-09-24
申请人： Takatoshi Yasui , Chiaki Kudo , Ichiro Nakao , Toyokazu Fujii , Yuka Terai , Shinichi Imai , Hiroshi Yamamoto , Yasushi Naito
发明人： Takatoshi Yasui , Chiaki Kudo , Ichiro Nakao , Toyokazu Fujii , Yuka Terai , Shinichi Imai , Hiroshi Yamamoto , Yasushi Naito
IPC分类号： H01L21/3105 , H01L21/768 , H01L21/00 , H01L21/02 , H01L21/324 , H01L21/477
CPC分类号： H01L21/76819 , H01L21/3105 , Y10S148/133 , Y10S438/909
摘要： Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.
摘要翻译：描述了一种用于制造半导体器件的方法，其包括根据预定温度分布以预定间距对安装在船上的半导体衬底进行加热和冷却的热处理工艺，以便通过回流绝缘膜来平坦化每个半导体衬底的表面含有杂质，例如在基板上形成的BPSG膜。在热处理过程中，设定影响绝缘膜中含有杂质的晶粒或颗粒形成的控制因素之一，以防止杂质在热处理过程中产生晶粒或颗粒。还公开了通过扩大安装的基板的间距来防止颗粒或颗粒的产生的方法。

4. 发明授权

US5278448A Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5278448A
公开(公告)日：1994-01-11
申请号：US853536
申请日：1992-03-18
申请人： Toyokazu Fujii
发明人： Toyokazu Fujii
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L21/44
CPC分类号： H01L21/76834 , H01L21/76843 , H01L21/7685 , H01L21/76867 , H01L21/76876 , H01L21/76877 , H01L23/532 , H01L2924/0002 , Y10S438/927
摘要： A semiconductor device has a multilayered metalization including a CVD tungsten film, a thin buffer layer deposited on the CVD tungsten film by sputtering, and an Al-alloy layer formed on the buffer layer. Due to the existence of the thin buffer layer, the crystal grains of the Al-alloy layer do not become small and the electromigration resistance as wiring is enhanced.
摘要翻译：半导体器件具有包括CVD钨膜，通过溅射沉积在CVD钨膜上的薄缓冲层和形成在缓冲层上的Al合金层的多层金属化。由于薄缓冲层的存在，Al合金层的晶粒不变小，并且作为布线的电迁移阻力增强。

5. 发明授权

US5104826A Method for fabricating semiconductor integrated circuit device using an electrode wiring structure 失效
标题翻译：使用电极布线结构制造半导体集成电路器件的方法
公开(公告)号：US5104826A
公开(公告)日：1992-04-14
申请号：US470579
申请日：1990-01-26
申请人： Tsutomu Fujita , Toyokazu Fujii
发明人： Tsutomu Fujita , Toyokazu Fujii
IPC分类号： H01L23/52 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/28556 , H01L21/76844 , H01L21/76847 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： In a CVD contact formed on a shallow junction having a depth of 0.2 micron or less, the presence of aluminum generates a leakage current at the junction after heat treatment. In order to restrain the leakage current, a barrier metal is formed below the aluminum electrode to form an Al/barrier metal/CVDW (tungsten) structure. A contact free from junction leakage and having a high aspect ratio is thereby realized.
摘要翻译：在深度为0.2微米以下的浅结上形成的CVD接触中，铝的存在在热处理后的接合处产生泄漏电流。为了抑制漏电流，在铝电极下形成阻挡金属，形成Al /阻挡金属/ CVDW（钨）结构。从而实现了没有结漏的高纵横比的接触。

6. 发明授权

US5451261A Metal film deposition apparatus and metal film deposition method 失效
标题翻译：金属膜沉积装置和金属膜沉积方法
公开(公告)号：US5451261A
公开(公告)日：1995-09-19
申请号：US114144
申请日：1993-09-01
申请人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
发明人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
IPC分类号： C23C14/04 , C23C16/04 , H01L21/00 , H01L21/677 , C23C16/00
CPC分类号： H01L21/67167 , C23C14/042 , C23C16/042 , H01L21/67207 , H01L21/67225 , H01L21/67796 , H01L2223/54473 , H01L2223/5448 , Y10S438/975
摘要： On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.
摘要翻译：在半导体基板上，形成从半导体基板的周边部分留出的成为产品的芯片和位于其一部分的对准芯片。在作为产品的芯片和对准芯片上形成接触孔和对准标记。用衬底保持器的对准标记覆盖部分覆盖对准芯片，在半导体衬底上沉积用于金属布线的材料，以在衬底上形成金属膜。使用未形成金属膜的取向芯片的对准标记，在金属膜上形成掩模图案。

7. 发明授权

US5355010A Semiconductor device with a dual type polycide layer comprising a uniformly p-type doped silicide 失效
标题翻译：具有双重型多晶硅化物层的半导体器件包括均匀的p型掺杂的硅化物
公开(公告)号：US5355010A
公开(公告)日：1994-10-11
申请号：US900993
申请日：1992-06-18
申请人： Toyokazu Fujii , Yasushi Naito
发明人： Toyokazu Fujii , Yasushi Naito
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8238 , H01L23/532 , H01L23/48 , H01L29/46 , H01L29/54
CPC分类号： H01L21/76889 , H01L21/28061 , H01L21/823842 , H01L23/53271 , H01L2924/0002
摘要： A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a polycide film including a polysilicon layer and a silicide layer formed on the insulating film. The polysilicon layer includes a p-type region having p-type impurities diffused therein and an n-type region having n-type impurities diffused therein. The p-type impurities are implanted into the silicide layer in order to have a substantially uniform concentration over the entire potion thereof, so that the p-type impurities in the p-type region of the polysilicon layer do not diffuse into the silicide film by a poet heat treatment.
摘要翻译：一种半导体器件，包括半导体衬底，形成在半导体衬底上的绝缘膜和在绝缘膜上形成的包括多晶硅层和硅化物层的多晶硅膜。多晶硅层包括在其中扩散有p型杂质的p型区域和在其中扩散n型杂质的n型区域。将p型杂质注入到硅化物层中，以便在其整个部分具有基本上均匀的浓度，使得多晶硅层的p型区域中的p型杂质不会通过以下方式扩散到硅化物膜中：诗人热处理。

8. 发明授权

US5939132A Alignment chips positioned in the peripheral part of the semiconductor substrate and method of manufacturing thereof 失效
标题翻译：定位在半导体衬底的周边部分的对准芯片及其制造方法
公开(公告)号：US5939132A
公开(公告)日：1999-08-17
申请号：US833193
申请日：1997-04-14
申请人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
发明人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
IPC分类号： C23C14/04 , C23C16/04 , H01L21/00 , H01L21/677 , B05D5/12 , H07L21/301
CPC分类号： H01L21/67167 , C23C14/042 , C23C16/042 , H01L21/67207 , H01L21/67225 , H01L21/67796 , H01L2223/54473 , H01L2223/5448 , Y10S438/975
摘要： On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.
摘要翻译：在半导体基板上，形成从半导体基板的周边部分留出的成为产品的芯片和位于其一部分的对准芯片。在作为产品的芯片和对准芯片上形成接触孔和对准标记。用衬底保持器的对准标记覆盖部分覆盖对准芯片，在半导体衬底上沉积用于金属布线的材料，以在衬底上形成金属膜。使用未形成金属膜的取向芯片的对准标记，在金属膜上形成掩模图案。

9. 发明授权

US5341014A Semiconductor device and a method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5341014A
公开(公告)日：1994-08-23
申请号：US989347
申请日：1992-12-11
申请人： Toyokazu Fujii , Yasushi Naito
发明人： Toyokazu Fujii , Yasushi Naito
IPC分类号： H01L21/3215 , H01L21/768 , H01L23/532 , H01L27/092 , H01L29/43 , H01L23/48 , H01L21/44
CPC分类号： H01L21/32155 , H01L21/76889 , H01L23/53271 , H01L27/0928 , H01L29/43 , H01L2924/0002
摘要： A semiconductor device of the present invention includes a semiconductor substrate, a p-type impurity diffused region formed in the semiconductor substrate, and a polycide interconnection electrically connected to the p-type impurity diffused region. In the semiconductor device, the polycide interconnection includes a first polysilicon film, a refractory metal silicide film formed on the first polysilicon film, and a second polysilicon film formed on the refractory metal silicide film.
摘要翻译：本发明的半导体器件包括半导体衬底，形成在半导体衬底中的p型杂质扩散区域和与p型杂质扩散区域电连接的多晶硅互连。在半导体器件中，多晶硅互连包括形成在第一多晶硅膜上的第一多晶硅膜，难熔金属硅化物膜和形成在难熔金属硅化物膜上的第二多晶硅膜。

10. 发明授权

US5705845A Semiconductor device with particular metal silicide film 失效
标题翻译：具有特殊金属硅化物膜的半导体器件
公开(公告)号：US5705845A
公开(公告)日：1998-01-06
申请号：US435479
申请日：1995-05-05
申请人： Toyokazu Fujii
发明人： Toyokazu Fujii
IPC分类号： H01L21/768 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/76889
摘要： In a metal silicide film, excessive silicon is contained and precipitated in silicide grain boundaries thereof. The thus precipitated excessive silicon makes a diffusion path of impurities, which extends along WSi.sub.2 grain interfaces, discontinuous in the metal silicide film. As a result, the impurities do not diffuse laterally in the metal silicide film even after a heat treatment is performed.
摘要翻译：在金属硅化物膜中，在其硅化物晶界中含有过量的硅并析出。这样沉淀的过量的硅使得在金属硅化物膜中不连续的沿着WSi2晶粒界面延伸的杂质的扩散路径。结果，即使在进行热处理之后，杂质也不会在金属硅化物膜中横向扩散。

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