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1. 发明授权

US07863753B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07863753B2
公开(公告)日：2011-01-04
申请号：US11896997
申请日：2007-09-07
申请人： Chiaki Kudo , Hisashi Ogawa
发明人： Chiaki Kudo , Hisashi Ogawa
IPC分类号： H01L29/41
CPC分类号： H01L29/42376 , H01L21/28123 , H01L21/823456 , H01L21/82385 , H01L27/0207 , H01L29/4238
摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.
摘要翻译：半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区; 以及形成在所述隔离区域和所述有源区域上并且包括所述隔离区域上的第一区域的第一栅电极。第一区域具有比有源区域上的第一栅电极的图案宽度大的栅极长度方向的图案宽度。第一区域包括具有与活性区域上的第一栅电极的膜厚度不同的膜厚度的部分。

2. 发明授权

US07636494B2 Method and apparatus for correcting pixel image signal intensity 失效
标题翻译：用于校正像素图像信号强度的方法和装置
公开(公告)号：US07636494B2
公开(公告)日：2009-12-22
申请号：US11003735
申请日：2004-12-06
申请人： Chiaki Kudo
发明人： Chiaki Kudo
IPC分类号： G06K9/40
CPC分类号： H04N5/372 , H04N5/3675 , H04N5/3728
摘要： When charges Q (x, y) transferred from an image inputting device 1 are to be converted into first signal intensities S′ (x, y) and signal processing is to be performed for the first signal intensity S′ (x, y) of a particular pixel, a maximum value Smax, a minimum value Smin and an average value Save are calculated from signal intensities S′ (x−1, y) and S′ (x+1, y) at adjacent pixels. When S′ (x, y)>Smax×A is satisfied, it is determined that the signal intensity S (x, y) at the particular pixel=Save×C (where A and C are coefficients), whereas when S′ (x, y)
摘要翻译：当从图像输入装置1传送的电荷Q（x，y）被转换为第一信号强度S'（x，y）时，对第一信号强度S'（x，y）进行信号处理根据相邻像素处的信号强度S'（x-1，y）和S'（x + 1，y）计算特定像素，最大值Smax，最小值Smin和平均值Save。当满足S'（x，y）> SmaxxA时，确定特定像素处的信号强度S（x，y）= SavexC（其中A和C是系数），而当S'（x，y）确定信号强度S（x，y）= SavexD（其中B和D是系数），并且执行处理以获得适当的强度S（x，y）

3. 发明授权

US06346736B1 Trench isolated semiconductor device 有权
标题翻译：沟槽隔离半导体器件
公开(公告)号：US06346736B1
公开(公告)日：2002-02-12
申请号：US09469498
申请日：1999-12-22
申请人： Takaaki Ukeda , Chiaki Kudo , Toshiki Yabu
发明人： Takaaki Ukeda , Chiaki Kudo , Toshiki Yabu
IPC分类号： H01L3300
CPC分类号： H01L23/5222 , H01L21/76232 , H01L2924/0002 , H01L2924/00
摘要： The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film. What results is a semiconductor device having lower total wiring-to-substrate capacitance and a higher operating speed.
摘要翻译： P型半导体衬底的顶表面被划分为有源区域，以形成元件和围绕有源区域的隔离区域。隔离区域由沟槽部分和虚拟半导体部分组成。在基板上沉积层间绝缘膜，然后在其上形成线。在每个半导体部分中，与将离子注入到元件中同时形成杂质扩散层，使得在杂质扩散层和硅衬底之间形成PN结。通过将杂质扩散层中的电容串联添加到层间绝缘膜中的电容而获得包含半导体部分的区域中的布线对基板电容的电容分量，该电容小于仅在中间层绝缘膜。具有较低的总布线对基板电容和更高的运行速度的半导体器件的结果是什么。

4. 发明申请

US20080073733A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080073733A1
公开(公告)日：2008-03-27
申请号：US11819192
申请日：2007-06-26
申请人： Chiaki Kudo , Yoshihiro Sato
发明人： Chiaki Kudo , Yoshihiro Sato
IPC分类号： H01L21/3205 , H01L21/336 , H01L29/76
CPC分类号： H01L21/823443 , H01L21/28097 , H01L21/823425 , H01L21/823456 , H01L21/823468 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a MIS transistor having a gate electrode which is fully silicided with metal. The edge parts of the gate electrode are lower in height than the other part thereof. Sidewall spacers are formed to cover the side and top surfaces of the edge parts of the gate electrode.
摘要翻译：半导体器件包括具有完全用金属硅化的栅电极的MIS晶体管。栅电极的边缘部分的高度低于其他部分。形成侧壁间隔件以覆盖栅电极的边缘部分的侧表面和顶表面。

5. 发明申请

US20050048764A1 Method of generating interconnection pattern 失效
标题翻译：产生互连模式的方法
公开(公告)号：US20050048764A1
公开(公告)日：2005-03-03
申请号：US10923869
申请日：2004-08-24
申请人： Chiaki Kudo
发明人： Chiaki Kudo
IPC分类号： G03F1/68 , G03F1/70 , G06F17/50 , H01L21/3205 , H01L21/4763 , H01L21/768 , H01L21/82 , H01L23/52 , H01L23/522
CPC分类号： G06F17/5077 , Y10S438/942
摘要： In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.
摘要翻译：在互连掩模图案生成中，通过使用用于半导体器件等的单个最小线宽数据生成的互连图案，抑制了互连的可靠性的降低和制造成品率的降低。当生成基于逻辑电路数据布置连接功能元件的互连的掩模上的布局布线图案时，基于最小线宽数据生成布线图形，基于最小线间距的互连图案然后生成数据，并且生成在它们两者的中间布置新的互连边界的互连图案以用作最终互连图案，使得互连图案宽度变得适当地变宽，从而使得可以提高互连的可靠性，抑制制造成品率的下降。

6. 发明授权

US6130139A Method of manufacturing trench-isolated semiconductor device 失效
标题翻译：制造沟槽隔离半导体器件的方法
公开(公告)号：US6130139A
公开(公告)日：2000-10-10
申请号：US978137
申请日：1997-11-25
申请人： Takaaki Ukeda , Chiaki Kudo , Toshiki Yabu
发明人： Takaaki Ukeda , Chiaki Kudo , Toshiki Yabu
IPC分类号： H01L21/762 , H01L23/522 , H01L21/76
CPC分类号： H01L23/5222 , H01L21/76232 , H01L2924/0002
摘要： The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film. What results is a semiconductor device having lower total wiring to-substrate capacitance and a higher operating speed.
摘要翻译： P型半导体衬底的顶表面被划分为有源区域，以形成元件和围绕有源区域的隔离区域。隔离区域由沟槽部分和虚拟半导体部分组成。在基板上沉积层间绝缘膜，然后在其上形成线。在每个半导体部分中，与将离子注入到元件中同时形成杂质扩散层，使得在杂质扩散层和硅衬底之间形成PN结。通过将杂质扩散层中的电容串联添加到层间绝缘膜中的电容而获得包含半导体部分的区域中的布线对基板电容的电容分量，该电容仅小于相互之间的电容层绝缘膜。具有较低的总布线对衬底电容和较高工作速度的半导体器件的结果是什么。

7. 发明授权

US07495299B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07495299B2
公开(公告)日：2009-02-24
申请号：US11544611
申请日：2006-10-10
申请人： Kazuhiko Aida , Junji Hirase , Hisashi Ogawa , Chiaki Kudo
发明人： Kazuhiko Aida , Junji Hirase , Hisashi Ogawa , Chiaki Kudo
IPC分类号： H01L29/78
CPC分类号： H01L21/82345 , H01L21/823437 , H01L21/823443 , H01L27/0207 , H01L29/665
摘要： The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebetween and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.
摘要翻译：执行以下步骤：在半导体衬底上形成栅电极，其间插入栅极绝缘膜，在半导体衬底上形成具有虚拟栅绝缘膜的虚拟栅电极，并在半导体衬底上形成另一虚拟栅电极其间插入有用于隔离的绝缘膜; 在半导体上形成金属膜，同时露出栅电极并覆盖伪栅电极; 对半导体基板进行热处理，至少使栅电极的上部被硅化。由于栅电极是硅化的，并且虚拟栅电极是非硅化的，所以这抑制了在栅电极和相邻的一个虚拟栅电极之间的短路。

8. 发明申请

US20080067574A1 Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080067574A1
公开(公告)日：2008-03-20
申请号：US11819190
申请日：2007-06-26
申请人： Chiaki Kudo
发明人： Chiaki Kudo
IPC分类号： H01L29/788 , H01L21/44
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/823871
摘要： A semiconductor device includes a first conductor and a second conductor electrically connected to each other to have the same potential. At least one of the first and second conductors has a fully silicided (FUSI) structure. A step having an overhang is formed at least at part of a boundary between the first and second conductors.
摘要翻译：半导体器件包括彼此电连接以具有相同电位的第一导体和第二导体。第一和第二导体中的至少一个具有完全硅化（FUSI）结构。至少在第一和第二导体之间的边界的一部分处形成具有突出端的台阶。

9. 发明授权

US06982222B2 Method of generating interconnection pattern 失效
标题翻译：产生互连模式的方法
公开(公告)号：US06982222B2
公开(公告)日：2006-01-03
申请号：US10923869
申请日：2004-08-24
申请人： Chiaki Kudo
发明人： Chiaki Kudo
IPC分类号： H01L21/4763
CPC分类号： G06F17/5077 , Y10S438/942
摘要： In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.
摘要翻译：在互连掩模图案生成中，通过使用用于半导体器件等的单个最小线宽数据生成的互连图案，抑制了互连的可靠性的降低和制造成品率的降低。当生成基于逻辑电路数据布置连接功能元件的互连的掩模上的布局布线图案时，基于最小线宽数据生成布线图形，基于最小线间距的互连图案然后生成数据，并且生成在它们两者的中间布置新的互连边界的互连图案以用作最终互连图案，使得互连图案宽度变得适当地变宽，从而使得可以提高互连的可靠性，抑制制造成品率的下降。

10. 发明授权

US06621123B1 Semiconductor device, and semiconductor integrated device 失效
标题翻译：半导体器件和半导体集成器件
公开(公告)号：US06621123B1
公开(公告)日：2003-09-16
申请号：US09576436
申请日：2000-05-22
申请人： Takashi Nakabayashi , Chiaki Kudo
发明人： Takashi Nakabayashi , Chiaki Kudo
IPC分类号： H01L2701
CPC分类号： H01L29/0649 , H01L29/66772 , H01L29/78606 , H01L29/78654 , H01L29/78696
摘要： On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.
摘要翻译：在P型硅的半导体基板上，沿着栅极宽度包括具有较小尺寸的沟道形成区域和沿着栅极长度延伸的源极区域和漏极区域的有源区域形成为被隔离区域包围的绝缘氧化膜。在半导体衬底上的隔离区域和有源区的沟道形成区域之间形成栅电极，栅极绝缘氧化膜夹在其间。在半导体衬底的有源区域中，仅在与用于隔离区域的绝缘氧化物膜相同的绝缘氧化膜的沟道下绝缘层仅在栅电极下方的沟道形成区域之下的区域中形成。

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