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1. 发明授权

US5451261A Metal film deposition apparatus and metal film deposition method 失效
标题翻译：金属膜沉积装置和金属膜沉积方法
公开(公告)号：US5451261A
公开(公告)日：1995-09-19
申请号：US114144
申请日：1993-09-01
申请人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
发明人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
IPC分类号： C23C14/04 , C23C16/04 , H01L21/00 , H01L21/677 , C23C16/00
CPC分类号： H01L21/67167 , C23C14/042 , C23C16/042 , H01L21/67207 , H01L21/67225 , H01L21/67796 , H01L2223/54473 , H01L2223/5448 , Y10S438/975
摘要： On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.
摘要翻译：在半导体基板上，形成从半导体基板的周边部分留出的成为产品的芯片和位于其一部分的对准芯片。在作为产品的芯片和对准芯片上形成接触孔和对准标记。用衬底保持器的对准标记覆盖部分覆盖对准芯片，在半导体衬底上沉积用于金属布线的材料，以在衬底上形成金属膜。使用未形成金属膜的取向芯片的对准标记，在金属膜上形成掩模图案。

2. 发明授权

US5939132A Alignment chips positioned in the peripheral part of the semiconductor substrate and method of manufacturing thereof 失效
标题翻译：定位在半导体衬底的周边部分的对准芯片及其制造方法
公开(公告)号：US5939132A
公开(公告)日：1999-08-17
申请号：US833193
申请日：1997-04-14
申请人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
发明人： Toyokazu Fujii , Mikio Nishio , Mitsuru Sekiguchi , Kazuhiko Hashimoto
IPC分类号： C23C14/04 , C23C16/04 , H01L21/00 , H01L21/677 , B05D5/12 , H07L21/301
CPC分类号： H01L21/67167 , C23C14/042 , C23C16/042 , H01L21/67207 , H01L21/67225 , H01L21/67796 , H01L2223/54473 , H01L2223/5448 , Y10S438/975
摘要： On a semiconductor substrate, chips to be products and alignment chips located at a portion a part thereof is left out from a peripheral part of the semiconductor substrate are formed. Contact holes and alignment marks are formed at the chips to be products and the alignment chips. Covering the alignment chips with alignment mark cover parts of a substrate holder, a material for metal wiring is deposited on the semiconductor substrate to form a metal film on the substrate. A mask pattern is formed on the metal film using the alignment marks of the alignment chips on which the metal film is not formed.
摘要翻译：在半导体基板上，形成从半导体基板的周边部分留出的成为产品的芯片和位于其一部分的对准芯片。在作为产品的芯片和对准芯片上形成接触孔和对准标记。用衬底保持器的对准标记覆盖部分覆盖对准芯片，在半导体衬底上沉积用于金属布线的材料，以在衬底上形成金属膜。使用未形成金属膜的取向芯片的对准标记，在金属膜上形成掩模图案。

3. 发明申请

US20090053522A1 TRIPLE-LAYER SEMICONDUCTOR NANOPARTICLE AND TRIPLE-LAYER SEMICONDUCTOR NANOROD 有权
标题翻译：三层半导体纳米粒子和三层半导体纳米级
公开(公告)号：US20090053522A1
公开(公告)日：2009-02-26
申请号：US12162164
申请日：2006-11-27
申请人： Mitsuru Sekiguchi , Kazuya Tsukada , Hisatake Okada
发明人： Mitsuru Sekiguchi , Kazuya Tsukada , Hisatake Okada
IPC分类号： B32B5/00 , B32B5/16
CPC分类号： C09K11/7442 , B22F1/0025 , B82Y30/00 , C01B21/0632 , C01G15/00 , C01G28/02 , C01G30/002 , C01P2002/84 , C01P2004/16 , C01P2004/30 , C01P2004/64 , C01P2004/84 , C01P2006/40 , C09K11/62 , C22C1/0491 , Y10S977/774 , Y10S977/813 , Y10S977/815 , Y10S977/825 , Y10S977/832 , Y10T428/24942 , Y10T428/2933 , Y10T428/2991
摘要： A semiconductor nanoparticle and semiconductor nanorod that have optical characteristics (luminescence intensity and emission lifetime) superior to those of conventional core/shell nanosized semiconductors. There are provided a triple-layer semiconductor nanoparticle, and triple-layer semiconductor nanorod, having an average particle diameter of 2 to 50 nm and comprising a core layer, an interlayer and a shell layer, wherein the layers are composed of different crystals, and wherein the crystal constructing the shell layer exhibits a band gap greater than that of the crystal constructing the core layer, and wherein the crystal constructing the interlayer has a lattice constant assuming a value between those of the crystal constructing the core layer and the crystal constructing the shell layer.
摘要翻译：具有优于常规核/壳纳米尺寸半导体的光学特性（发光强度和发光寿命）的半导体纳米颗粒和半导体纳米棒。提供平均粒径为2〜50nm的三层半导体纳米颗粒和三层半导体纳米棒，其包含芯层，中间层和壳层，其中层由不同的晶体构成，并且其中，构成壳层的晶体的表面带隙大于构成芯层的晶体的带隙，构成中间层的晶体的晶体晶格常数为假定构成芯层的晶体的构成晶格常数与构成芯层的晶体的晶格常数壳层。

4. 发明申请

US20080116381A1 SCINTILLATOR PANEL, METHOD OF MANUFACTURING THE SAME AND RADIATION IMAGING APPARATUS 有权
标题翻译：扫描仪面板，其制造方法和放射成像装置
公开(公告)号：US20080116381A1
公开(公告)日：2008-05-22
申请号：US11942365
申请日：2007-11-19
申请人： Masashi KONDO , Takehiko Shoji , Mitsuru Sekiguchi
发明人： Masashi KONDO , Takehiko Shoji , Mitsuru Sekiguchi
IPC分类号： G21K4/00 , G01T1/20 , B05D5/06
CPC分类号： G21K4/00
摘要： A scintillator panel comprising: a radiation-transparent substrate; and a phosphor layer provided on the substrate, the phosphor layer emitting light when irradiated with a radiation, wherein at least one edge of the substrate and at least one edge of the phosphor layer are arranged on a same plane.
摘要翻译：一种闪烁体面板，包括：辐射透明衬底; 以及设置在所述基板上的荧光体层，所述荧光体层在用辐射照射时发光，其中所述基板的至少一个边缘和所述荧光体层的至少一个边缘布置在同一平面上。

5. 发明申请

US20050035457A1 Interconnecting structure with dummy vias 审中-公开
标题翻译：互连结构与虚拟通孔
公开(公告)号：US20050035457A1
公开(公告)日：2005-02-17
申请号：US10791751
申请日：2004-03-04
申请人： Kazuo Tomita , Keiji Hashimoto , Yasutaka Nishioka , Susumu Matsumoto , Mitsuru Sekiguchi , Akihisa Iwasaki
发明人： Kazuo Tomita , Keiji Hashimoto , Yasutaka Nishioka , Susumu Matsumoto , Mitsuru Sekiguchi , Akihisa Iwasaki
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/02
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： First wirings and first dummy wirings are in a p-SiOC film on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.
摘要翻译：第一布线和第一虚拟布线在基板上的p-SiOC膜中。形成p-SiOC膜，在p-SiOC膜上形成盖膜。在盖膜和p-SiOC膜22中形成包括连接到第一布线和第二布线的通孔的双镶嵌布线。在隔离的通孔的周边上形成有通孔。

6. 发明授权

US06407954B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06407954B2
公开(公告)日：2002-06-18
申请号：US09781829
申请日：2001-02-12
申请人： Kazuhisa Ninomiya , Mitsuru Sekiguchi
发明人： Kazuhisa Ninomiya , Mitsuru Sekiguchi
IPC分类号： G11C700
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454
摘要： A nonvolatile semiconductor memory device comprises a plurality of sectors each having a plurality of memory cell arrays, a controller which responds to an address signal and a control signal to activate at least one of the sectors; and a plurality of data comparing circuits provided in the memory cell arrays, respectively, the data comparing circuits each which latches a write data to be written the respective memory cell arrays and compares the write data latched and a data read out from the respective memory cell arrays to produce a comparison result. The controller activates all of the sectors when the control signal has a first logic level regardless of levels of the address signal so that write data is written into the memory cell arrays of the sectors activated. The controller activates the sectors in sequence in response to changing levels of the address signal when the control signal has a second logic level to output the comparison results from the data comparing circuits in sequence.
摘要翻译：非易失性半导体存储器件包括多个扇区，每个扇区各自具有多个存储单元阵列;响应地址信号的控制器和控制信号以激活至少一个扇区; 以及分别设置在存储单元阵列中的多个数据比较电路，每个数据比较电路锁存写入数据以写入各个存储单元阵列的数据比较电路，并比较锁存的写入数据和从各个存储单元读出的数据数组产生比较结果。当控制信号具有第一逻辑电平而无论地址信号的电平如何，控制器激活所有扇区，使得写入数据被写入被激活的扇区的存储单元阵列中。当控制信号具有第二逻辑电平时，响应于地址信号的变化电平，控制器按顺序激活扇区，从而顺序地从数据比较电路输出比较结果。

7. 发明授权

US06272045B1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06272045B1
公开(公告)日：2001-08-07
申请号：US09527825
申请日：2000-03-17
申请人： Mitsuru Sekiguchi
发明人： Mitsuru Sekiguchi
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/26
摘要： A nonvolatile semiconductor memory device has writing signal line selecting transistors for applying writing signals to memory elements, respectively, reading signal line selecting transistors for delivering reading signals from the memory elements, respectively, and bit line selecting transistors connected between the writing signal line selecting transistors or the reading signal line selecting transistors and the memory elements, for selecting bit lines of each of the memory elements.
摘要翻译：非易失性半导体存储器件分别具有写入信号线选择晶体管，用于分别向存储元件施加写入信号，分别读取用于从存储元件传送读取信号的信号线选择晶体管，以及连接在写入信号线选择晶体管或读取信号线选择晶体管和存储器元件，用于选择每个存储元件的位线。

8. 发明申请

US20120001282A1 RADIATION DETECTOR 失效
标题翻译：辐射探测器
公开(公告)号：US20120001282A1
公开(公告)日：2012-01-05
申请号：US13256052
申请日：2010-02-23
申请人： Narito Goto , Mitsuru Sekiguchi
发明人： Narito Goto , Mitsuru Sekiguchi
IPC分类号： H01L31/115
CPC分类号： G01T1/2018 , C09K11/628 , G21K4/00 , G21K2004/06
摘要： A radiation detector of a compact size and producing almost no image defect is disclosed, comprising a first radiation-transmissive substrate, a first adhesive layer, a second radiation-transmissive substrate, a scintillator layer and an output substrate provided with a photoelectric conversion element layer which are provided sequentially in this order, wherein an arrangement region of the scintillator layer in a planar direction of the layer includes an arrangement region of the photoelectric conversion element layer in a planar direction of the layer and an arrangement region of the first substrate in a planar direction of the substrate, and the arrangement region of the first substrate includes the arrangement region of the photoelectric conversion element layer; and when the arrangement region of the scintillator layer is divided to plural areas, a coefficient of variation of filling factor is 20% or less which is defined as a standard deviation of filling factor of phosphor of the plural areas, divided by an average value of the filling factor.
摘要翻译：公开了一种紧凑尺寸并且几乎不产生图像缺陷的辐射检测器，包括第一辐射透射基板，第一粘合层，第二辐射透射基板，闪烁体层和设置有光电转换元件层的输出基板其顺序地依次提供，其中闪烁体层在层的平面方向上的布置区域包括在该层的平面方向上的光电转换元件层的布置区域和第一基板的布置区域基板的平面方向，第一基板的配置区域包括光电转换元件层的配置区域; 并且当闪烁体层的排列区域被划分为多个区域时，填充系数的变化系数为20％以下，其被定义为多个区域的荧光体的填充系数的标准偏差除以平均值填充因子。

9. 发明申请

US20080149852A1 MANUFACTURING METHOD OF SCINTILLATOR PANEL, SCINTILLATOR PANEL AND VACUUM EVAPORATION APPARATUS 审中-公开
标题翻译：扫描板，喷涂板和真空蒸发装置的制造方法
公开(公告)号：US20080149852A1
公开(公告)日：2008-06-26
申请号：US11945965
申请日：2007-11-27
申请人： Takehiko Shoji , Mitsuru Sekiguchi
发明人： Takehiko Shoji , Mitsuru Sekiguchi
IPC分类号： G21K4/00 , B29C65/64
CPC分类号： G21K4/00 , B29C65/38 , B29C66/001 , B29C66/433 , B29C66/71 , B29C66/72321 , B29C66/82661 , B29K2001/00 , B29K2001/12 , B29K2067/00 , C23C14/0694 , G01T1/202 , G21K2004/10 , Y10T156/1052 , Y10T156/12 , B29K2083/00 , B29K2079/08 , B29K2077/00 , B29K2075/02 , B29K2075/00 , B29K2067/003 , B29K2063/00 , B29K2061/04 , B29K2033/08 , B29K2027/06 , B29K2023/12 , B29K2019/00 , B29K2009/06 , B29K2001/18
摘要： A method of manufacturing a scintillator panel comprising the sequential steps of: forming an electroconductive metal reflection layer on a polymer film substrate; forming a protective layer on the electroconductive metal reflection layer; cutting the polymer film substrate having thereon the electroconductive metal reflection layer and the protective layer into a prescribed size; forming a scintillator layer by a vacuum evaporation method on the protective layer of the polymer film substrate cut in the prescribed size to prepare a scintillator sheet; and sealing the scintillator sheet with sealing films provided above and below the scintillator sheet to prepare the scintillator panel, wherein static electricity is removed from the polymer film substrate through a cut surface of the electroconductive metal reflection layer when the scintillator layer is vacuum evaporated.
摘要翻译：一种制造闪烁体面板的方法，包括以下顺序步骤：在聚合物薄膜基底上形成导电金属反射层; 在导电金属反射层上形成保护层; 将其上具有导电金属反射层和保护层的聚合物膜基材切割成规定尺寸; 通过真空蒸发法在以规定尺寸切割的聚合物膜基材的保护层上形成闪烁体层，以制备闪烁体片; 并用闪烁体片上方和下方设置的密封膜密封闪烁体片以制备闪烁体面板，其中当闪烁体层被真空蒸发时，通过导电金属反射层的切割表面从聚合物膜基底上去除静电。

10. 发明申请

US20080054181A1 SCINTILLATOR PLATE, MANUFACTURING METHOD OF THE SAME AND RADIATION IMAGE SENSOR 有权
标题翻译：扫描板，其制造方法和辐射图像传感器
公开(公告)号：US20080054181A1
公开(公告)日：2008-03-06
申请号：US11846312
申请日：2007-08-28
申请人： Masashi Kondo , Yasushi Nagata , Mitsuru Sekiguchi
发明人： Masashi Kondo , Yasushi Nagata , Mitsuru Sekiguchi
IPC分类号： G01T1/20
CPC分类号： G01T1/202
摘要： A scintillator plate comprising: (i) a radiation transmissive substrate; (ii) a light absorbing layer formed on the substrate, the light absorbing layer absorbing light of a prescribed wavelength range; and (iii) a scintillator layer formed on the light absorbing layer, the scintillator layer converting radiation to the light having a wavelength absorbable to the light absorbing layer.
摘要翻译：一种闪烁体板，包括：（i）辐射透射基底; （ii）形成在所述基板上的光吸收层，所述光吸收层吸收规定波长范围的光; 和（iii）形成在光吸收层上的闪烁体层，所述闪烁体层将辐射转换成具有可吸收光吸收层的波长的光。

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