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1. 发明授权

US06534354B1 Method of manufacturing MOS transistor with fluorine implantation at a low energy 有权
标题翻译：以低能量制造氟注入的MOS晶体管的方法
公开(公告)号：US06534354B1
公开(公告)日：2003-03-18
申请号：US10004635
申请日：2001-12-04
申请人： Tong-Hsin Lee , Terry Chung-Yi Chen
发明人： Tong-Hsin Lee , Terry Chung-Yi Chen
IPC分类号： H01L218238
CPC分类号： H01L29/665 , H01L21/265 , H01L27/11 , Y10S438/919
摘要： A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.
摘要翻译：一种制造MOS晶体管的方法。提供了具有栅极氧化物层，栅电极和附着到栅电极的侧壁的间隔物的衬底。进行源极/漏极（S / D）注入以在栅电极的每一侧上的衬底中形成源极/漏极区域。进行自对准硅化物（硅化物）工艺以在暴露的栅极电极和源极/漏极区域上形成自对准的硅化物层。在衬底上形成用作蚀刻停止层的氮化硅层。氮化硅蚀刻停止层的氟化物覆盖层注入使用约5×10 13〜5×10 14 cm -2的注入剂量和2KeV〜5KeV之间的注入能级进行。注入氮化硅层的氟化物捕获氮化硅层内的氢，从而降低自由氢浓度并增加MOS晶体管的阈值电压稳定性。

2. 发明授权

US6093600A Method of fabricating a dynamic random-access memory device 失效
标题翻译：制造动态随机存取存储器件的方法
公开(公告)号：US6093600A
公开(公告)日：2000-07-25
申请号：US430706
申请日：1999-10-29
申请人： Terry Chung-Yi Chen , Tong-Hsin Lee
发明人： Terry Chung-Yi Chen , Tong-Hsin Lee
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10835 , H01L27/10861 , H01L21/76895 , H01L28/60
摘要： A method of fabricating a dynamic random-access memory (DRAM) device integrates a shallow trench isolation (STI) process and a storage node process into the fabrication of the DRAM device. With a bit line over capacitor (BOC) structure, the capacitor is laid out in parts of the shallow trench isolation structure to increase the surface area of the storage node by using the trench. During the fabrication of the capacitor, a stacked plug used to connect the bit line is formed. The stacked plug used as the interconnection in the circuit region is also formed. An insulating layer is formed to cover the capacitor, and an opening is formed therein to expose the stacked plug. A bit line and an interconnection are formed on the insulating layer to connect with a conducting layer which is located in the stacked plug and contacted with the source/drain regions.
摘要翻译：制造动态随机存取存储器（DRAM）器件的方法将浅沟槽隔离（STI）处理和存储节点处理集成到DRAM器件的制造中。通过在电容器（BOC）结构上的位线，电容器布置在浅沟槽隔离结构的部分中，以通过使用沟槽来增加存储节点的表面积。在制造电容器期间，形成用于连接位线的堆叠式插头。还形成了用作电路区域中的互连的堆叠插头。形成绝缘层以覆盖电容器，并且在其中形成开口以露出堆叠的插塞。在绝缘层上形成位线和互连，以与位于堆叠式插头中并与源极/漏极区域接触的导电层连接。

3. 发明授权

US06300238B1 Method of fabricating node contact opening 失效
标题翻译：节点接触开口的制作方法
公开(公告)号：US06300238B1
公开(公告)日：2001-10-09
申请号：US09390104
申请日：1999-09-03
申请人： Tong-Hsin Lee , Terry Chung-Yi Chen
发明人： Tong-Hsin Lee , Terry Chung-Yi Chen
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814
摘要： A fabrication method of a node contact opening involves forming a first insulating layer on the substrate, in which a bit line, which contacts the substrate, is formed on the first insulating layer. A conformal second insulating layer that serves as an etching stop layer is formed after the formation of bit line. A third insulating layer is then formed to isolate the subsequently formed capacitor and bit line. A pattern mask is formed on the third insulating layer, while a pattern of the pattern mask is transferred into the third insulating layer, so that an opening is formed in the third insulating layer. After the second insulating layer in the opening is removed, a spacer is formed on a sidewall of the opening. With the pattern mask and the spacer serving as an etching mask, the first insulating layer below the bit line is etched until the opening is extended through to the substrate, so that a contact opening is formed.
摘要翻译：节点接触开口的制造方法包括在衬底上形成第一绝缘层，其中在第一绝缘层上形成接触衬底的位线。在形成位线之后形成用作蚀刻停止层的保形第二绝缘层。然后形成第三绝缘层以隔离随后形成的电容器和位线。在第三绝缘层上形成图形掩模，同时将图案掩模的图案转移到第三绝缘层中，从而在第三绝缘层中形成开口。在开口中的第二绝缘层被去除之后，在开口的侧壁上形成间隔物。利用图案掩模和间隔件作为蚀刻掩模，蚀刻位线下方的第一绝缘层直到开口延伸到基板，从而形成接触开口。

4. 发明授权

US06569726B1 Method of manufacturing MOS transistor with fluoride implantation on silicon nitride etching stop layer 有权
标题翻译：在氮化硅蚀刻停止层上制造具有氟化物注入的MOS晶体管的方法
公开(公告)号：US06569726B1
公开(公告)日：2003-05-27
申请号：US10154604
申请日：2002-05-22
申请人： Tong-Hsin Lee , Terry Chung-Yi Chen
发明人： Tong-Hsin Lee , Terry Chung-Yi Chen
IPC分类号： H01L218238
CPC分类号： H01L29/665 , H01L21/265 , H01L27/11 , Y10S438/919
摘要： A method of manufacturing a MOS transistor. A substrate having a gate oxide layer, a gate electrode and spacers attached to the sidewalls of the gate electrode is provided. A source/drain (S/D) implantation is conducted to form a source/drain region in the substrate on each side of the gate electrode. A self-aligned silicide (Salicide) process is carried out to form a self-aligned silicide layer over the exposed gate electrode and source/drain region. A silicon nitride layer serving as an etching stop is formed over the substrate. A fluoride blanket implantation of the silicon nitride etching stop layer is carried out using an implantation dosage of about 5×1013 ˜5×1014 cm−2 and at an implantation energy level between 2 KeV˜5 KeV. The fluorides implanted into the silicon nitride layer capture hydrogen within the silicon nitride layer, thereby reducing free hydrogen concentration and increasing threshold voltage stability of the MOS transistor.
摘要翻译：一种制造MOS晶体管的方法。提供了具有栅极氧化物层，栅电极和附着到栅电极的侧壁的间隔物的衬底。进行源极/漏极（S / D）注入以在栅电极的每一侧上的衬底中形成源极/漏极区域。进行自对准硅化物（硅化物）工艺以在暴露的栅极电极和源极/漏极区域上形成自对准的硅化物层。在衬底上形成用作蚀刻停止层的氮化硅层。氮化硅蚀刻停止层的氟化物覆盖层注入使用约5×10 13〜5×10 14 cm -2的注入剂量和2KeV〜5KeV之间的注入能级进行。注入氮化硅层的氟化物捕获氮化硅层内的氢，从而降低自由氢浓度并增加MOS晶体管的阈值电压稳定性。

5. 发明授权

US06207579B1 Method of fabricating self-aligned node 失效
标题翻译：制造自对准节点的方法
公开(公告)号：US06207579B1
公开(公告)日：2001-03-27
申请号：US09286357
申请日：1999-04-05
申请人： Terry Chung-Yi Chen
发明人： Terry Chung-Yi Chen
IPC分类号： H01L213065
CPC分类号： H01L27/10885 , H01L21/76877 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L28/75
摘要： A method of fabricating a self-aligned storage node is described. A storage node plug is formed after formations of the bit line contact and the storage node contact. A spacer is formed on a sidewall of an opening, which is used for forming a bit line. The bit line is formed in the opening. Because the spacer provides good isolation, the tolerance window for forming the bit line is increased. Some follow-up steps are performed to form a storage node.
摘要翻译：描述了制造自对准存储节点的方法。在位线接触和存储节点接触的结构之后形成存储节点插头。间隔件形成在用于形成位线的开口的侧壁上。位线在开口处形成。因为间隔物提供良好的隔离，所以用于形成位线的公差窗口增加。执行一些后续步骤以形成存储节点。

6. 发明授权

US06194266B1 Method for forming a capacitor having selective hemispherical grained polysilicon 有权
标题翻译：用于形成具有选择性半球形多晶硅的电容器的方法
公开(公告)号：US06194266B1
公开(公告)日：2001-02-27
申请号：US09511656
申请日：2000-02-22
申请人： Terry Chung-Yi Chen , Cheng-Chih Kung , Da-Wen Hsia , Cheng-Chieh Huang
发明人： Terry Chung-Yi Chen , Cheng-Chih Kung , Da-Wen Hsia , Cheng-Chieh Huang
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L27/10852 , Y10S438/964
摘要： A method for forming a capacitor containing selective hemispherical grained (S-HSG) polysilicon is disclosed. In this invention, dopant implantation is incorporated after the S-HSG growth to replace conventional wet clean procedure. The elimination of the cleaning treatments avoids the incidents of residue particles (due to cleaning) and minimizes numerous structure defects. The incorporation of the ion implantation technique would make up the insufficiency of doping requirement by applying in-diffusion alone. The combination of the in-diffusion and the implantation for doping procedure could maintain the device with good capacitance level even though the pre-clean procedure is excluded.
摘要翻译：公开了一种形成包含选择性半球晶粒（S-HSG）多晶硅的电容器的方法。在本发明中，在S-HSG生长之后掺入掺杂剂注入以代替常规的湿式清洁程序。消除清洁处理可以避免残留颗粒的发生（由于清洁），并最大限度地减少许多结构缺陷。离子注入技术的并入将通过单独使用扩散扩散来弥补掺杂需求的不足。扩散和掺杂过程的注入的组合可以保持器件具有良好的电容水平，即使排除了预清洁程序。

7. 发明授权

US06200890B1 Method of fabricating copper damascene 失效
标题翻译：铜镶嵌方法
公开(公告)号：US06200890B1
公开(公告)日：2001-03-13
申请号：US09372433
申请日：1999-08-10
申请人： Terry Chung-Yi Chen
发明人： Terry Chung-Yi Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A fabrication method for a copper (Cu) damascene, involving etching a part of a dielectric layer after formation of the Cu conducting wires, so that the Cu conducting wires project out from the surface of the dielectric layer. A top barrier layer is formed to prevent Cu electromigration (EM) and current leakage.
摘要翻译：一种铜（Cu）镶嵌体的制造方法，包括在形成Cu导线之后蚀刻介电层的一部分，使得Cu导线从介电层的表面突出。形成顶部阻挡层以防止Cu电迁移（EM）和电流泄漏。

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