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1. 发明授权

US4990973A Method of producing an MMIC and the integrated circuit produced thereby 失效
标题翻译：制造MMIC的方法和由此产生的集成电路
公开(公告)号：US4990973A
公开(公告)日：1991-02-05
申请号：US436615
申请日：1989-11-15
申请人： Takahide Ishikawa , Kazuhiko Nakahara
发明人： Takahide Ishikawa , Kazuhiko Nakahara
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8232 , H01L27/06 , H01L27/095 , H03F1/30 , H03F3/195 , H03F3/60
CPC分类号： H01L27/0605 , H03F1/306
摘要： A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.

2. 发明授权

US06911837B2 Method and apparatus for evaluating and adjusting microwave integrated circuit 失效
标题翻译：微波集成电路评估与调试方法及装置
公开(公告)号：US06911837B2
公开(公告)日：2005-06-28
申请号：US10893371
申请日：2004-07-19
申请人： Takahide Ishikawa , Yoshitsugu Yamamoto , Tetsuo Kunii , Satoshi Suzuki , Hirotaka Amasuga
发明人： Takahide Ishikawa , Yoshitsugu Yamamoto , Tetsuo Kunii , Satoshi Suzuki , Hirotaka Amasuga
IPC分类号： H01L21/288 , H01L21/3205 , H01L21/48 , H01L21/66 , H01L23/66 , G01R31/26
CPC分类号： H01L22/22 , H01L21/485 , H01L23/66 , H01L2924/0002 , H01L2924/15173 , H01L2924/00
摘要： The present method includes steps of: discharging a droplet of fluid containing fine particles with electric characteristics from an inkjet nozzle onto the microwave integrated circuit formed on a substrate; forming a coat of the fine particles having electric characteristics on the substrate; measuring electric characteristics of the microwave integrated circuit using a probe of a circuit evaluation apparatus before and after forming the coat; and adjusting the electric characteristics of the microwave integrated circuit, so that forming the coat at a desired location on the upper surface of the circuit substrate by scanning an aim of the inkjet nozzle against the circuit substrate enables the microwave integrated circuit to meet the specification.
摘要翻译：本方法包括以下步骤：将含有电特性的细颗粒的液滴从喷墨喷嘴喷射到形成在基板上的微波集成电路上; 在基板上形成具有电特性的微粒的涂层; 使用电路评估装置的探针在形成涂层之前和之后测量微波集成电路的电特性; 并且调整微波集成电路的电特性，使得通过将喷墨喷嘴的目标扫过电路基板而在电路基板的上表面上的期望位置处形成涂层，使得微波集成电路能够满足规格。

3. 发明授权

US5932926A Microwave semiconductor integrated circuit 失效
标题翻译：微波半导体集成电路
公开(公告)号：US5932926A
公开(公告)日：1999-08-03
申请号：US795790
申请日：1997-02-05
申请人： Takaya Maruyama , Takahide Ishikawa , Noriyuki Tanino
发明人： Takaya Maruyama , Takahide Ishikawa , Noriyuki Tanino
IPC分类号： H01L23/12 , H01L23/66 , H01L23/34
CPC分类号： H01L23/66 , H01L2223/6627 , H01L2224/45144 , H01L2224/48227 , H01L2924/1903
摘要： A microwave semiconductor integrated circuit having high isolation includes a wiring-side substrate including a transmission line in slots at a surface; an element-side substrate having an active element on a surface, the transmission line being embedded in the wiring-side substrate; and metal bumps electrically connecting the transmission line embedded in the wiring-side substrate to electrodes of the active element on the element-side substrate. Therefore, a connection between a transmission line and electrodes of an element, such as an FET or the like, can be easily realized without being affected by a difference in positional level between the transmission line and the electrodes. In addition, the element on the element-side substrate is not adversely affected by the subsequent fabrication of the slots and wiring layers and, therefore, the reliability of the integrated circuit is not adversely affected. Furthermore, since the element and the transmission line are mounted on separate substrates, focusing is easy during the exposure for forming masks used for etching the slots and wiring layers in the wiring-side substrate because there is no unevenness within the substrate surface, facilitating the fabrication of masks.
摘要翻译：具有高隔离度的微波半导体集成电路包括在表面的槽中包括传输线的布线侧基板; 元件侧基板，其表面上具有有源元件，所述传输线嵌入在所述布线侧基板中; 以及金属凸块将嵌入在布线侧基板中的传输线与元件侧基板上的有源元件的电极电连接。因此，可以容易地实现传输线和诸如FET等的元件的电极之间的连接，而不受传输线和电极之间的位置水平差的影响。此外，元件侧基板上的元件不受后续制造槽和布线层的不利影响，因此集成电路的可靠性不受不利影响。此外，由于元件和传输线安装在单独的基板上，因为在基板表面中没有不均匀性，因此在用于形成用于蚀刻布线侧基板中的槽和布线层的掩模的曝光期间，聚焦容易，制作面具。

4. 发明授权

US5812364A Capacitor 失效
标题翻译：电容器
公开(公告)号：US5812364A
公开(公告)日：1998-09-22
申请号：US782671
申请日：1997-01-15
申请人： Tomoki Oku , Takahide Ishikawa
发明人： Tomoki Oku , Takahide Ishikawa
IPC分类号： H01G4/33 , H01L21/822 , H01L27/04 , H01L29/94 , H01G4/06 , H01G4/12 , H01G4/20
CPC分类号： H01L29/94
摘要： An MIM capacitor includes a lower electrode; a first insulating film disposed on the lower electrode; a second insulating film disposed on the first insulating film and having a first opening exposing a portion of the surface of the first insulating film on the lower electrode, the first opening having a perimeter; a third insulating film disposed on the second insulating film and having a second opening exposing a portion of the surface of the second insulating film, the second opening having a perimeter that surrounds the perimeter of the first opening on the second insulating film; and an upper electrode disposed on the first insulating film through the first opening and extending onto the second insulating film.
摘要翻译： MIM电容器包括下电极; 设置在下电极上的第一绝缘膜; 第二绝缘膜，设置在所述第一绝缘膜上，并且具有第一开口，所述第一开口暴露所述下电极上的所述第一绝缘膜的所述表面的一部分，所述第一开口具有周边; 第三绝缘膜，其设置在所述第二绝缘膜上并且具有暴露所述第二绝缘膜表面的一部分的第二开口，所述第二开口具有围绕所述第二绝缘膜上的所述第一开口的周边的周边; 以及通过第一开口设置在第一绝缘膜上并延伸到第二绝缘膜上的上电极。

5. 发明授权

US5324981A Field effect transistor device with contact in groove 失效
标题翻译：场效应晶体管器件与沟槽接触
公开(公告)号：US5324981A
公开(公告)日：1994-06-28
申请号：US46920
申请日：1993-04-14
申请人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
发明人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
IPC分类号： H01L23/52 , H01L21/301 , H01L21/3205 , H01L21/74 , H01L21/78 , H01L23/00 , H01L23/36 , H01L23/48 , H01L23/58
CPC分类号： H01L22/32 , H01L21/743 , H01L21/78 , H01L23/36 , H01L23/481 , H01L23/562 , H01L2924/0002 , Y10S148/028 , Y10S438/977
摘要： A high power FET device includes a plated heat sink, a rear surface electrode disposed between a substrate and the heat sink, a via-hole extending through the substrate and containing a metal plating for electrically connecting the rear surface electrode and an element, such as the source electrode, of the FET device. A metallic layer extending from the rear surface to the front surface of the device protects the side walls of the substrate during handling. The side wall protection layer extends onto portions of the front surface of the substrate as a measurement electrode. The arrangement gives access to the source, drain, and gate electrodes of the device from the front surface for measuring the electrical characteristics of the device while it is still part of a wafer containing a large number of devices. Each device includes a separation groove outwardly spaced from the device and containing a metallic layer which becomes the side wall protection layer after dicing. Preferably, the separation grooves are wider and deeper than the via-holes.
摘要翻译：高功率FET器件包括电镀散热器，设置在基板和散热片之间的背面电极，延伸穿过基板的通孔，并容纳用于电连接背面电极和元件的金属镀层，例如 FET器件的源电极。从设备的后表面延伸到前表面的金属层在处理期间保护基板的侧壁。侧壁保护层作为测量电极延伸到基板的前表面的部分上。该布置允许从前表面访问器件的源极，漏极和栅电极，用于测量器件的电特性，同时它仍然是包含大量器件的晶片的一部分。每个装置包括与装置向外间隔的分离槽，并且包含在切割之后成为侧壁保护层的金属层。优选地，分离槽比通孔更宽和更深。

6. 发明授权

US5302554A Method for producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5302554A
公开(公告)日：1994-04-12
申请号：US928026
申请日：1992-08-11
申请人： Takuo Kashiwa , Takahide Ishikawa , Yoshihiro Notani
发明人： Takuo Kashiwa , Takahide Ishikawa , Yoshihiro Notani
IPC分类号： H01L21/301 , H01L21/304 , H01L21/302
CPC分类号： H01L21/3043 , H01L21/304 , Y10S148/028
摘要： According to a method for producing semiconductor chips, grooves serving as dicing lines are formed in a front surface of a semiconductor wafer, the semiconductor wafer is ground from the rear surface to a prescribed thickness, leaving portions of the wafer opposite the grooves, a feeding layer is formed on the ground rear surface of the wafer, a metal layer for heat radiation is formed on the feeding layer, a dicing tape is applied to the metal layer, and the wafer and the feeding layer are diced along the dicing lines, resulting in a plurality of semiconductor chips. Therefore, the strength of the wafer is increased because portions of the wafer remain at the dicing lines, preventing curvature of the wafer. When a plurality of metal layers for heat radiation are selectively formed on the feeding layer except for regions opposite the dicing lines, since only thin portions of the wafer and the feeding layer are present at the dicing lines, burrs produced during dicing are reduced and an adequate junction is achieved in a subsequent die-bonding process.
摘要翻译：根据半导体芯片的制造方法，在半导体晶片的正面形成有用作切割线的槽，将半导体晶片从后表面研磨成规定的厚度，使晶片的与槽相反的一部分，层形成在晶片的接地后表面上，在馈电层上形成用于散热的金属层，将切割带施加到金属层，并且沿着切割线切割晶片和馈电层，导致在多个半导体芯片中。因此，由于晶片的部分保留在切割线处，因此晶片的强度增加，从而防止了晶片的弯曲。当除了与切割线相对的区域之外，在供给层上选择性地形成多个用于散热的金属层时，由于在切割线处仅存在晶片和馈电层的薄部分，所以在切割期间产生的毛刺减少，并且在随后的芯片接合工艺中实现足够的连接。

7. 发明授权

US5275958A Method for producing semiconductor chips 失效
标题翻译：半导体芯片的制造方法
公开(公告)号：US5275958A
公开(公告)日：1994-01-04
申请号：US4058
申请日：1993-01-13
申请人： Takahide Ishikawa
发明人： Takahide Ishikawa
IPC分类号： H01L21/301 , H01L21/78 , H01L21/302
CPC分类号： H01L21/78 , H01L2224/29101 , Y10S148/028 , Y10S148/05 , Y10S148/135
摘要： According to a method for producing semiconductor chips, first grooves are formed in a semiconductor wafer at a front surface, dividing the semiconductor water into a plurality of regions, each region including a single device or an integrated circuit; a first metallization layer is formed in the first grooves; the semiconductor wafer is thinned to a desired thickness from the rear surface of the wafer; second grooves are formed in the semiconductor wafer at the rear surface at positions opposite the first grooves, exposing the first metallization layer; a second metallization layer is formed in the second grooves; a metal layer for heat radiation is formed on the rear surface of the wafer but not on the second metallization layer; and the first and second metallization layers in the first grooves are cut with a dicing blade to produce a plurality of semiconductor chips. Burrs of the metallization layers caused by the dicing are small and never protrude beyond the rear surface of the chip, resulting in a reliable junction between the chip and a mounting substrate in a subsequent die-bonding process.
摘要翻译：根据制造半导体芯片的方法，在前表面的半导体晶片中形成第一凹槽，将半导体水分割为多个区域，每个区域包括单个器件或集成电路; 在第一凹槽中形成第一金属化层; 半导体晶片从晶片的后表面变薄到所希望的厚度; 在所述半导体晶片中的与所述第一凹槽相对的位置的后表面处形成第二凹槽，暴露所述第一金属化层; 在第二槽中形成第二金属化层; 在晶片的后表面上形成用于散热的金属层，但不形成在第二金属化层上; 并且用切割刀片切割第一凹槽中的第一和第二金属化层以产生多个半导体芯片。由切割引起的金属化层的毛刺小，并且不会突出超过芯片的后表面，导致在随后的芯片接合工艺中芯片和安装基板之间的可靠连接。

8. 发明授权

US4921814A Method of producing an MMIC 失效
标题翻译：生产MMIC的方法
公开(公告)号：US4921814A
公开(公告)日：1990-05-01
申请号：US289210
申请日：1988-12-22
申请人： Takahide Ishikawa , Kazuhiko Nakahara
发明人： Takahide Ishikawa , Kazuhiko Nakahara
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8232 , H01L27/06 , H01L27/095 , H03F1/30 , H03F3/195 , H03F3/60
CPC分类号： H01L27/0605 , H03F1/306
摘要： A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.
摘要翻译：在相同的偏压条件下，生产MMIC和MMIC的方法具有可批次的静态工作点。如果栅极凹槽的深度随批次而变化，则MMIC中放大器MESFET的漏极饱和电流源可能会随批次而异。因此，在相同偏置条件下，放大器的静态工作点可以随批次而变化。与放大器MESFET同时地制造补偿栅极偏置源，优选地在MMIC上以额外的MESFET的形式，因此具有与放大器MESFET的深度精确匹配的深度的栅极凹槽。额外的MESFET作为补偿栅极偏置源连接，具有作为栅极凹槽深度的函数的电阻，从而补偿放大器MESFET的静态工作点。

9. 发明授权

US06271619B1 Piezoelectric thin film device 失效
标题翻译：压电薄膜器件
公开(公告)号：US06271619B1
公开(公告)日：2001-08-07
申请号：US09423538
申请日：1999-11-12
申请人： Akira Yamada , Chisako Maeda , Toshio Umemura , Fusaoki Uchikawa , Koichiro Misu , Shusou Wadaka , Takahide Ishikawa
发明人： Akira Yamada , Chisako Maeda , Toshio Umemura , Fusaoki Uchikawa , Koichiro Misu , Shusou Wadaka , Takahide Ishikawa
IPC分类号： H01L4104
CPC分类号： H03H9/174 , H03H3/02 , H03H9/131 , H03H9/173
摘要： A piezoelectric thin film device which is composed mainly of a substrate, a piezoelectric thin film formed on the substrate, and thin film electrodes formed on both the upper and lower surfaces of the thin film. The thin film is resonated by applying an AC voltage across the electrodes. A substrate removed section is formed by partially or entirely removing the substrate below the thin film and opened to both the front and rear surfaces of the substrate through openings so as to relieve the pressure variation in the substrate removed section below a resonant structure.
摘要翻译：主要由基板，形成在基板上的压电薄膜和形成在薄膜的上表面和下表面上的薄膜电极组成的压电薄膜器件。通过在电极之间施加交流电压来使薄膜谐振。基板去除部分通过部分地或全部地去除薄膜下方的基板并且通过开口对基板的前表面和后表面打开而形成，以便减轻谐振结构之下的基板去除部分中的压力变化。

10. 发明授权

US4956697A Microwave monolithic integrated circuit with heat radiating electrode 失效
标题翻译：具有散热电极的微波单片集成电路
公开(公告)号：US4956697A
公开(公告)日：1990-09-11
申请号：US251677
申请日：1988-09-30
申请人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
发明人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
IPC分类号： H01L23/34 , C03B29/06 , C03B35/16 , C03B35/18 , F16C13/00 , H01L21/822 , H01L23/66 , H01L27/04 , H01L27/06
CPC分类号： C03B29/06 , C03B35/165 , C03B35/181 , F16C13/00 , H01L23/66 , H01L24/24 , H01L24/82 , H01L27/0605 , H01L2224/24225 , H01L2224/24226 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/0104 , H01L2924/01057 , H01L2924/01058 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01088 , H01L2924/10329 , H01L2924/13063 , H01L2924/14 , H01L2924/1423 , H01L2924/3011 , Y10S148/05 , Y10S148/051 , Y10S148/135 , Y10S438/928 , Y10S438/977
摘要： A microwave monolithic integrated circuit comprising a GaAs substrate having upper and lower opposed surfaces, an active region and at least one passive region produced on the upper surface of the substrate, and a heat sink produced on the lower surface of the substrate, wherein the substrate thickness beneath the active region is smaller than the substrate thickness beneath at least one passive region, thereby disposing the heat sink near the active region to improve heat dissipation therefrom. The active region and the passive regions are separated by intermediate areas and the substrate thickness beneath the intermediate areas is smaller than the substrate thickness beneath the active region such that the heat sink at least partially surrounds the substrate beneath the active region. Each passive region is associated with a respective microwave transmission line having a predetermined width and a desired characteristic impedance and the thickness of the substrate beneath each of the passive regions is established individually based on the width and the desired characteristic impedance of each respective microwave transmission line.
摘要翻译：一种微波单片集成电路，包括具有上和下相对表面的GaAs衬底，在衬底的上表面上产生的有源区和至少一个无源区，以及在衬底的下表面上产生的散热器，其中衬底有源区下方的厚度小于至少一个无源区下面的衬底厚度，从而将散热器设置在有源区附近，以改善散热。有源区域和无源区域由中间区域分开，并且中间区域下方的衬底厚度小于有源区域下面的衬底厚度，使得散热器至少部分地围绕有源区域下方的衬底。每个无源区域与具有预定宽度和期望特性阻抗的相应微波传输线相关联，并且基于每个相应的微波传输线的宽度和期望的特性阻抗分别建立每个无源区下的衬底的厚度。

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