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1. 发明授权

US06271619B1 Piezoelectric thin film device 失效
标题翻译：压电薄膜器件
公开(公告)号：US06271619B1
公开(公告)日：2001-08-07
申请号：US09423538
申请日：1999-11-12
申请人： Akira Yamada , Chisako Maeda , Toshio Umemura , Fusaoki Uchikawa , Koichiro Misu , Shusou Wadaka , Takahide Ishikawa
发明人： Akira Yamada , Chisako Maeda , Toshio Umemura , Fusaoki Uchikawa , Koichiro Misu , Shusou Wadaka , Takahide Ishikawa
IPC分类号： H01L4104
CPC分类号： H03H9/174 , H03H3/02 , H03H9/131 , H03H9/173
摘要： A piezoelectric thin film device which is composed mainly of a substrate, a piezoelectric thin film formed on the substrate, and thin film electrodes formed on both the upper and lower surfaces of the thin film. The thin film is resonated by applying an AC voltage across the electrodes. A substrate removed section is formed by partially or entirely removing the substrate below the thin film and opened to both the front and rear surfaces of the substrate through openings so as to relieve the pressure variation in the substrate removed section below a resonant structure.
摘要翻译：主要由基板，形成在基板上的压电薄膜和形成在薄膜的上表面和下表面上的薄膜电极组成的压电薄膜器件。通过在电极之间施加交流电压来使薄膜谐振。基板去除部分通过部分地或全部地去除薄膜下方的基板并且通过开口对基板的前表面和后表面打开而形成，以便减轻谐振结构之下的基板去除部分中的压力变化。

2. 发明授权

US4990973A Method of producing an MMIC and the integrated circuit produced thereby 失效
标题翻译：制造MMIC的方法和由此产生的集成电路
公开(公告)号：US4990973A
公开(公告)日：1991-02-05
申请号：US436615
申请日：1989-11-15
申请人： Takahide Ishikawa , Kazuhiko Nakahara
发明人： Takahide Ishikawa , Kazuhiko Nakahara
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8232 , H01L27/06 , H01L27/095 , H03F1/30 , H03F3/195 , H03F3/60
CPC分类号： H01L27/0605 , H03F1/306
摘要： A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.

3. 发明授权

US4956697A Microwave monolithic integrated circuit with heat radiating electrode 失效
标题翻译：具有散热电极的微波单片集成电路
公开(公告)号：US4956697A
公开(公告)日：1990-09-11
申请号：US251677
申请日：1988-09-30
申请人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
发明人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
IPC分类号： H01L23/34 , C03B29/06 , C03B35/16 , C03B35/18 , F16C13/00 , H01L21/822 , H01L23/66 , H01L27/04 , H01L27/06
CPC分类号： C03B29/06 , C03B35/165 , C03B35/181 , F16C13/00 , H01L23/66 , H01L24/24 , H01L24/82 , H01L27/0605 , H01L2224/24225 , H01L2224/24226 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01033 , H01L2924/0104 , H01L2924/01057 , H01L2924/01058 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01088 , H01L2924/10329 , H01L2924/13063 , H01L2924/14 , H01L2924/1423 , H01L2924/3011 , Y10S148/05 , Y10S148/051 , Y10S148/135 , Y10S438/928 , Y10S438/977
摘要： A microwave monolithic integrated circuit comprising a GaAs substrate having upper and lower opposed surfaces, an active region and at least one passive region produced on the upper surface of the substrate, and a heat sink produced on the lower surface of the substrate, wherein the substrate thickness beneath the active region is smaller than the substrate thickness beneath at least one passive region, thereby disposing the heat sink near the active region to improve heat dissipation therefrom. The active region and the passive regions are separated by intermediate areas and the substrate thickness beneath the intermediate areas is smaller than the substrate thickness beneath the active region such that the heat sink at least partially surrounds the substrate beneath the active region. Each passive region is associated with a respective microwave transmission line having a predetermined width and a desired characteristic impedance and the thickness of the substrate beneath each of the passive regions is established individually based on the width and the desired characteristic impedance of each respective microwave transmission line.
摘要翻译：一种微波单片集成电路，包括具有上和下相对表面的GaAs衬底，在衬底的上表面上产生的有源区和至少一个无源区，以及在衬底的下表面上产生的散热器，其中衬底有源区下方的厚度小于至少一个无源区下面的衬底厚度，从而将散热器设置在有源区附近，以改善散热。有源区域和无源区域由中间区域分开，并且中间区域下方的衬底厚度小于有源区域下面的衬底厚度，使得散热器至少部分地围绕有源区域下方的衬底。每个无源区域与具有预定宽度和期望特性阻抗的相应微波传输线相关联，并且基于每个相应的微波传输线的宽度和期望的特性阻抗分别建立每个无源区下的衬底的厚度。

4. 发明申请

US20050046435A1 METHOD AND APPARATUS FOR EVALUATING AND ADJUSTING MICROWAVE INTEGRATED CIRCUIT 失效
标题翻译：用于评估和调整微波集成电路的方法和装置
公开(公告)号：US20050046435A1
公开(公告)日：2005-03-03
申请号：US10893371
申请日：2004-07-19
申请人： Takahide Ishikawa , Yoshitsugu Yamamoto , Tetsuo Kunii , Satoshi Suzuki , Hirotaka Amasuga
发明人： Takahide Ishikawa , Yoshitsugu Yamamoto , Tetsuo Kunii , Satoshi Suzuki , Hirotaka Amasuga
IPC分类号： H01L21/288 , H01L21/3205 , H01L21/48 , H01L21/66 , H01L23/66 , H01L29/06
CPC分类号： H01L22/22 , H01L21/485 , H01L23/66 , H01L2924/0002 , H01L2924/15173 , H01L2924/00
摘要： The present method includes steps of: discharging a droplet of fluid containing fine particles with electric characteristics from an inkjet nozzle onto the microwave integrated circuit formed on a substrate; forming a coat of the fine particles having electric characteristics on the substrate; measuring electric characteristics of the microwave integrated circuit using a probe of a circuit evaluation apparatus before and after forming the coat; and adjusting the electric characteristics of the microwave integrated circuit, so that forming the coat at a desired location on the upper surface of the circuit substrate by scanning an aim of the inkjet nozzle against the circuit substrate enables the microwave integrated circuit to meet the specification.
摘要翻译：本方法包括以下步骤：将含有电特性的细颗粒的液滴从喷墨喷嘴喷射到形成在基板上的微波集成电路上; 在基板上形成具有电特性的微粒的涂层; 使用电路评估装置的探针在形成涂层之前和之后测量微波集成电路的电特性; 并且调整微波集成电路的电特性，使得通过将喷墨喷嘴的目标扫过电路基板而在电路基板的上表面上的期望位置处形成涂层，使得微波集成电路能够满足规格。

5. 发明授权

US5652557A Transmission lines and fabricating method thereof 失效
标题翻译：传输线及其制造方法
公开(公告)号：US5652557A
公开(公告)日：1997-07-29
申请号：US544196
申请日：1995-10-17
申请人： Takahide Ishikawa
发明人： Takahide Ishikawa
IPC分类号： H01L21/3205 , H01L23/52 , H01L23/66 , H01P1/22 , H01P1/24 , H01P1/26 , H01P3/08 , H01P5/02 , H01P5/08 , H01P11/00 , H05K1/00
CPC分类号： H01P3/081 , H01L23/66 , H01P3/088 , H01L2223/6622 , H01L2223/6627 , H01L2924/1617 , H01L2924/1903 , H01L2924/3011
摘要： A transmission line including a dielectric or semi-insulating substrate; a groove in the substrate; a metallization film disposed on the bottom surface of the groove; a dielectric filling the groove and making contact with the metallization film; a wiring conductor film disposed on the dielectric; and a grounding metallization film disposed on the rear surface of the substrate. Excellent confinement of electromagnetic waves is achieved and electromagnetic wave interference between two neighboring lines is extremely small, realizing a high density arrangement of transmission lines and a compact and lightweight microwave/millimeter wave integrated circuit. Higher modes of electromagnetic wave propagation are avoided by controlling the thickness of the dielectric filling the groove while the thickness of the substrate remains arbitrary, thereby improving production yield and reliability.
摘要翻译：一种传输线，包括电介质或半绝缘衬底; 衬底中的凹槽; 设置在所述槽的底面上的金属化膜; 电介质填充凹槽并与金属化膜接触; 设置在电介质上的布线导体膜; 以及设置在基板的后表面上的接地金属化膜。实现电磁波的良好限制，两条相邻线路之间的电磁波干扰极小，实现了传输线的高密度布置和紧凑轻巧的微波/毫米波集成电路。通过控制填充凹槽的介质的厚度，同时基板的厚度保持任意来避免更高的电磁波传播模式，从而提高产量和可靠性。

6. 发明授权

US5270228A Method of fabricating gate electrode in recess 失效
标题翻译：在凹槽中制作栅电极的方法
公开(公告)号：US5270228A
公开(公告)日：1993-12-14
申请号：US745333
申请日：1991-08-15
申请人： Takahide Ishikawa
发明人： Takahide Ishikawa
IPC分类号： H01L21/306 , H01L21/338 , H01L29/812 , H01L21/265 , H01L21/44
CPC分类号： H01L29/66863
摘要： A method of fabricating a field effect transistor in which the gate electrode is formed in a multiple step recess including a first recess located on one level and a second recess located on a lower level. The second, narrower recess is nested in the first, wider recess. The method is initiated by growing a first semiconductor layer of a low etch rate on a semiconductor substrate. Then, a second semiconductor layer of a high etch rate is grown on the first semiconductor layer. A resist film having an opening in a selected location is formed on the second semiconductor layer. Using this resist film as a mask, the semiconductor layers are selectively etched. The gate electrode is formed at the bottom of the multiple step recess created by the etching.
摘要翻译：一种制造场效应晶体管的方法，其中栅极形成在包括位于一个层上的第一凹部和位于较低层上的第二凹槽的多级凹槽中。第二个更狭窄的凹槽嵌在第一个较宽的凹槽中。该方法通过在半导体衬底上生长低蚀刻速率的第一半导体层来启动。然后，在第一半导体层上生长高蚀刻速率的第二半导体层。在第二半导体层上形成具有选定位置的开口的抗蚀剂膜。使用该抗蚀剂膜作为掩模，选择性地蚀刻半导体层。栅电极形成在通过蚀刻产生的多级凹槽的底部。

7. 发明授权

US06998615B2 Method for evaluating piezoelectric fields 失效
标题翻译：压电场评估方法
公开(公告)号：US06998615B2
公开(公告)日：2006-02-14
申请号：US10768163
申请日：2004-02-02
申请人： Hideo Takeuchi , Yoshitsugu Yamamoto , Takahide Ishikawa
发明人： Hideo Takeuchi , Yoshitsugu Yamamoto , Takahide Ishikawa
IPC分类号： G01R29/22
CPC分类号： G01N21/35
摘要： In a method of evaluating a piezoelectric field, non-destructive spectrometry of piezoelectric fields is performed in a semiconductor heterojunction using a technique different from PR spectroscopy. In the method, at first, first and second absorption spectra are measured by irradiating the sample with infrared light at first and second angles, respectively. Then, a peak position of an absorption band having incident-angle dependent intensity is specified, based on the first and second absorption spectra. Thus, the piezoelectric field strength is obtained using a relationship between the piezoelectric field and an electron energy level corresponding to the peak position.
摘要翻译：在评估压电场的方法中，使用与PR光谱不同的技术在半导体异质结中进行压电场的非破坏性光谱测定。在该方法中，首先，通过分别以第一和第二角度以红外光照射样品来测量第一和第二吸收光谱。然后，基于第一吸收光谱和第二吸收光谱，确定具有入射角依赖强度的吸收带的峰值位置。因此，使用压电场和对应于峰值位置的电子能级之间的关系获得压电场强。

8. 发明授权

US5434094A Method of producing a field effect transistor 失效
标题翻译：制作场效应晶体管的方法
公开(公告)号：US5434094A
公开(公告)日：1995-07-18
申请号：US224882
申请日：1994-04-08
申请人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
发明人： Michihiro Kobiki , Masahiro Yoshida , Takahide Ishikawa
IPC分类号： H01L23/52 , H01L21/301 , H01L21/3205 , H01L21/74 , H01L21/78 , H01L23/00 , H01L23/36 , H01L23/48 , H01L23/58 , H01L21/8252
CPC分类号： H01L22/32 , H01L21/743 , H01L21/78 , H01L23/36 , H01L23/481 , H01L23/562 , H01L2924/0002 , Y10S148/028 , Y10S438/977
摘要： FET devices according to the invention are made by etching separation grooves and the via-holes from the front surface of the substrate. Thereafter, the thickness of the substrate is reduced from the rear surface to expose the plating in the via-holes and separation grooves. A rear surface electrode and a plated heat sink are sequentially deposited on the rear surface of the thinned substrate. The devices are divided from a wafer by etching and/or severing along the separation grooves and at opposed locations along the plated heat sink.
摘要翻译：根据本发明的FET器件通过从衬底的前表面蚀刻分离槽和通孔来制造。此后，基板的厚度从后表面减小，以露出通孔和分离槽中的电镀。背面电极和电镀散热片顺序地沉积在薄的衬底的后表面上。这些器件通过沿着分离槽的蚀刻和/或切割以及沿着镀覆的散热器的相对位置从晶片分割。

9. 发明授权

US5429994A Wiring forming method, wiring restoring method and wiring pattern changing method 失效
标题翻译：接线形成方法，布线恢复方法和布线图案改变方法
公开(公告)号：US5429994A
公开(公告)日：1995-07-04
申请号：US278338
申请日：1994-07-21
申请人： Takahide Ishikawa
发明人： Takahide Ishikawa
IPC分类号： H01L21/203 , C23C16/04 , H01L21/205 , H01L21/288 , H01L21/3205 , H01L21/768 , H05K3/14 , H05K3/22 , H01L21/02
CPC分类号： C23C16/047 , H01L21/288 , H01L21/76888 , H01L21/76892 , H05K3/146 , H05K3/225
摘要： In a method of manufacturing a semiconductor device, a metal film including a metal element is formed on a wiring base layer by ion beam assisted CVD, more specifically, by selectively irradiating a region of the wiring base layer with a focused ion beam while blowing an organic metal gas containing the metal element onto the region irradiated by the ion beam. Thereafter, a low-resistance metal layer is formed on the metal film by electroless plating. Therefore, a metal wiring of low resistivity with a predetermined pattern is formed without a photolithographic process using a resist and also without sputtering or selective etching of the metal film. Consequently, manufacturing costs of a semiconductor device are significantly reduced.
摘要翻译：在制造半导体器件的方法中，通过离子束辅助CVD在布线基底层上形成包括金属元素的金属膜，更具体地，通过用聚焦离子束选择性地照射布线基底层的区域，同时吹塑将含有金属元素的有机金属气体放置在由离子束照射的区域上。此后，通过化学镀在金属膜上形成低电阻金属层。因此，在不使用抗蚀剂的光刻工艺下，也不进行溅射或选择性蚀刻金属膜的情况下，形成具有预定图案的低电阻率的金属布线。因此，半导体器件的制造成本显着降低。

10. 发明授权

US5177026A Method for producing a compound semiconductor MIS FET 失效
标题翻译：化合物半导体MIS FET的制造方法
公开(公告)号：US5177026A
公开(公告)日：1993-01-05
申请号：US686831
申请日：1991-04-17
申请人： Takahide Ishikawa
发明人： Takahide Ishikawa
IPC分类号： H01L29/80 , H01L29/812
CPC分类号： H01L29/802 , H01L29/812
摘要： A compound semiconductor MIS FET includes a channel layer produced on a semi-insulating substrate with an intervening buffer layer, source and drain electrodes produced directly on a predetermined region of the channel layer, and a Schottky barrier gate electrode produced on the channel layer between the source and drain ohmic electrodes and on an undoped semiconductor layer. A production method for such a compound semiconductor MIS FET includes removing by etching undoped semiconductor layer at source and drain electrode production regions to expose a channel layer existing therebelow before producing the source and drain electrodes, and producing ohmic electrodes on the exposed channel layer and producing a Schottky barrier gate electrode between the source and drain electrodes on the undoped layer.
摘要翻译：化合物半导体MIS FET包括在半绝缘基板上制造的沟道层，其具有中间缓冲层，直接在沟道层的预定区域上产生的源极和漏极以及在沟道层之间产生的肖特基势垒栅电极源极和漏极欧姆电极以及未掺杂的半导体层。这种化合物半导体MIS FET的制造方法包括通过在源极和漏极生成区域处蚀刻未掺杂的半导体层来去除，以在产生源极和漏极之前露出存在于其的沟道层，并在暴露的沟道层上产生欧姆电极并产生在未掺杂层上的源极和漏极之间的肖特基势垒栅电极。

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