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1. 发明授权

US06719808B1 Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask 失效
标题翻译：使用多晶硅硬掩模制造半导体器件的方法和装置
公开(公告)号：US06719808B1
公开(公告)日：2004-04-13
申请号：US09695068
申请日：2000-10-25
申请人： Ji-soo Kim , Tae-hyuk Ahn , Won-seok Lee , Wan-jae Park
发明人： Ji-soo Kim , Tae-hyuk Ahn , Won-seok Lee , Wan-jae Park
IPC分类号： H01L21302
CPC分类号： H01L21/32137 , H01L21/31144
摘要： A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate. The processing apparatus includes a reaction chamber including a spin chuck which supports the semiconductor substrate for rotation, a gas supply unit for supplying a process gas to the reaction chamber, a gas injection unit for injecting the process gas supplied by the gas supply unit into the reaction chamber in a direction parallel to the major surface of the semiconductor substrate, and an exhaust unit for exhausting gases from the reaction chamber.
摘要翻译：用于制造半导体器件的方法和装置剥离多晶硅硬掩模，而不会损坏通过使用多晶硅硬掩模形成的开口暴露的层作为蚀刻掩模。该方法包括在第一层上形成图案中的多晶硅硬掩模以暴露第一层的一部分，使用多晶硅硬掩模作为蚀刻掩模干蚀刻第一层的暴露部分，以在第一层中形成开口然后通过在多晶硅硬掩模上沿着与半导体基板的主表面平行的方向提供蚀刻气体来除去多晶硅硬掩模。处理装置包括：反应室，包括支撑旋转用半导体基板的旋转卡盘，向反应室供给处理气体的气体供给单元，将由气体供给单元供给的处理气体注入到反应室在与半导体基板的主表面平行的方向上，以及用于从反应室排出气体的排气单元。

2. 发明授权

US06465346B2 Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask 有权
标题翻译：半导体器件的导线及其制造方法使用氧化铝层作为硬掩模
公开(公告)号：US06465346B2
公开(公告)日：2002-10-15
申请号：US09794617
申请日：2001-02-28
申请人： Ji-soo Kim , Wan-jae Park , Chang-woong Chu , Sang-hun Seo
发明人： Ji-soo Kim , Wan-jae Park , Chang-woong Chu , Sang-hun Seo
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/0332 , H01L21/31116 , H01L21/31122 , H01L21/31144 , H01L21/32139
摘要： A conducting line of a semiconductor device using an aluminum oxide layer as a hard mask, and a method of forming the conducting line. The conducting line, such as a gate line or a bit line of a semiconductor device, includes a conductive layer formed on a semiconductor substrate, a capping insulation layer formed on the conductive layer, and an aluminum oxide layer formed on the capping insulation layer, with the aluminum oxide layer being used as a hard mask.
摘要翻译：使用氧化铝层作为硬掩模的半导体器件的导线以及形成导线的方法。诸如半导体器件的栅极线或位线的导线包括形成在半导体衬底上的导电层，形成在导电层上的封盖绝缘层和形成在封盖绝缘层上的氧化铝层，其中氧化铝层用作硬掩模。

3. 发明授权

US07145140B2 Method of determining whether a conductive layer of a semiconductor device is exposed through a contact hold 失效
标题翻译：通过接触保持来确定半导体器件的导电层是否露出的方法
公开(公告)号：US07145140B2
公开(公告)日：2006-12-05
申请号：US10673581
申请日：2003-09-30
申请人： Ji-soo Kim , Wan-jae Park , Kyoung-sub Shin
发明人： Ji-soo Kim , Wan-jae Park , Kyoung-sub Shin
IPC分类号： G01N23/225
CPC分类号： H01J37/32935 , H01J37/266 , H01J2237/004 , H01J2237/2594
摘要： In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.
摘要翻译：在用于确定用于制造半导体器件的等离子体引起的充电程度的方法及其装置中，在其上进行了等离子体处理的晶片的表面上的预定区域被一次电子束。收集由一次电子束和晶片表面之间的反应产生的二次电子，这些二次电子被发射到晶片表面的外部。由等离子体工艺中使用的等离子体在晶片表面引起的充电程度由收集的二次电子量的变化确定。基于充电的程度来确定接触孔是打开还是关于栅极绝缘层的劣化程度。

4. 发明授权

US06657192B1 Method of determining degree of charge-up induced by plasma used for manufacturing semiconductor device and apparatus therefor 有权
标题翻译：确定用于制造半导体器件的等离子体引起的充电程度的方法及其装置
公开(公告)号：US06657192B1
公开(公告)日：2003-12-02
申请号：US09640088
申请日：2000-08-17
申请人： Ji-soo Kim , Wan-jae Park , Kyoung-sub Shin
发明人： Ji-soo Kim , Wan-jae Park , Kyoung-sub Shin
IPC分类号： G01N2300
CPC分类号： H01J37/32935 , H01J37/266 , H01J2237/004 , H01J2237/2594
摘要： In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.
摘要翻译：在用于确定用于制造半导体器件的等离子体引起的充电程度的方法及其装置中，在其上进行了等离子体处理的晶片的表面上的预定区域被一次电子束。收集由一次电子束和晶片表面之间的反应产生的二次电子，这些二次电子被发射到晶片表面的外部。由等离子体工艺中使用的等离子体在晶片表面引起的充电程度由收集的二次电子量的变化确定。基于充电的程度来确定接触孔是打开还是关于栅极绝缘层的劣化程度。

5. 发明申请

US20080070409A1 Method of Fabricating Interconnections of Microelectronic Device Using Dual Damascene Process 有权
标题翻译：使用双镶嵌工艺制造微电子器件互连的方法
公开(公告)号：US20080070409A1
公开(公告)日：2008-03-20
申请号：US11532719
申请日：2006-09-18
申请人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
发明人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/02271 , H01L21/31116 , H01L21/31144 , H01L21/31155 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L2221/1063 , Y10S438/924
摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.
摘要翻译：使用双镶嵌工艺制造微电子器件互连的方法。制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层层，并且用导电材料填充通孔和沟槽以形成上互连。

6. 发明授权

US08058176B2 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations 有权
标题翻译：使用补偿蚀刻速率变化的蚀刻技术对绝缘层进行图案化的方法
公开(公告)号：US08058176B2
公开(公告)日：2011-11-15
申请号：US11861478
申请日：2007-09-26
申请人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
发明人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
IPC分类号： H01L21/311
CPC分类号： H01L21/31116
摘要： Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.
摘要翻译：形成集成电路器件的方法包括在其上形成具有电绝缘层的集成电路衬底，并在电绝缘层上形成至少具有不同大小的第一和第二开口的掩模层图案。分别与第一和第二开口相对延伸的电绝缘层的第一和第二部分以第一和第二不同的蚀刻速率被同时蚀刻。该蚀刻产生相邻于第一开口延伸的第一沟槽，其比邻近第二开口延伸的第二沟槽更深。然后，使用补偿第一和第二不同蚀刻速率的蚀刻工艺，将第一和第二沟槽的底部同时蚀刻到基本上相同的深度。

7. 发明申请

US20090081873A1 Methods of Patterning Insulating Layers Using Etching Techniques that Compensate for Etch Rate Variations 有权
标题翻译：使用补偿蚀刻速率变化的蚀刻技术对绝缘层进行图案化的方法
公开(公告)号：US20090081873A1
公开(公告)日：2009-03-26
申请号：US11861478
申请日：2007-09-26
申请人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
发明人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
IPC分类号： H01L21/311
CPC分类号： H01L21/31116
摘要： Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.
摘要翻译：形成集成电路器件的方法包括在其上形成具有电绝缘层的集成电路衬底，并在电绝缘层上形成至少具有不同大小的第一和第二开口的掩模层图案。分别与第一和第二开口相对延伸的电绝缘层的第一和第二部分以第一和第二不同的蚀刻速率被同时蚀刻。该蚀刻产生相邻于第一开口延伸的第一沟槽，其比邻近第二开口延伸的第二沟槽更深。然后，使用补偿第一和第二不同蚀刻速率的蚀刻工艺，将第一和第二沟槽的底部同时蚀刻到基本上相同的深度。

8. 发明授权

US07229875B2 Integrated circuit capacitor structure 失效
标题翻译：集成电路电容器结构
公开(公告)号：US07229875B2
公开(公告)日：2007-06-12
申请号：US10688077
申请日：2003-10-16
申请人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Wan-jae Park , Jeong-hoon Ahn , Kyung-tae Lee , Mu-kyeng Jung , Yong-jun Lee , Il-goo Kim , Soo-geun Lee
IPC分类号： H01L21/8234
CPC分类号： H01L28/40 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.
摘要翻译：本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

9. 发明授权

US07183195B2 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler 有权
标题翻译：使用混合低k电介质和无碳无机填料制造微电子器件的双镶嵌互连的方法
公开(公告)号：US07183195B2
公开(公告)日：2007-02-27
申请号：US10625007
申请日：2003-07-23
申请人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
发明人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.
摘要翻译：提供了一种制造双镶嵌互连的方法。在具有3.3或更小的介电常数的混合电介质层中形成双镶嵌区域，并且使用无碳无机材料作为通孔填料。本发明改进了双镶嵌互连的电性能并使缺陷最小化。

10. 发明授权

US07553758B2 Method of fabricating interconnections of microelectronic device using dual damascene process 有权
标题翻译：使用双镶嵌工艺制造微电子器件互连的方法
公开(公告)号：US07553758B2
公开(公告)日：2009-06-30
申请号：US11532719
申请日：2006-09-18
申请人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
发明人： Wan-jae Park , Hyung-yoon Choi , Yi-hsiung Lin , Tong Qing Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/3146 , H01L21/02115 , H01L21/0212 , H01L21/02167 , H01L21/02271 , H01L21/31116 , H01L21/31144 , H01L21/31155 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L2221/1063 , Y10S438/924
摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.
摘要翻译：使用双镶嵌工艺制造微电子器件互连的方法。制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层层，并且用导电材料填充通孔和沟槽以形成上互连。

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