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1. 发明授权

US06590434B2 Delay time controlling circuit and method for controlling delay time 失效
公开(公告)号：US06590434B2
公开(公告)日：2003-07-08
申请号：US10191413
申请日：2002-07-10
申请人： Hoe-ju Chung , Tae-seong Jang , Kyu-hyoun Kim
发明人： Hoe-ju Chung , Tae-seong Jang , Kyu-hyoun Kim
IPC分类号： H03H1126
CPC分类号： G11C29/028 , G11C7/22 , G11C7/222 , G11C29/02 , G11C29/50012 , G11C2207/2254 , H03K5/133 , H03K2005/00091 , H03L7/0814
摘要： A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

2. 发明授权

US5946269A Synchronous RAM controlling device and method 失效
标题翻译：同步RAM控制装置及方法
公开(公告)号：US5946269A
公开(公告)日：1999-08-31
申请号：US156345
申请日：1998-09-18
申请人： Tae-seong Jang
发明人： Tae-seong Jang
IPC分类号： G11C11/413 , G11C7/10 , G11C8/04 , G11C11/407 , H03M7/00 , G11C8/00
CPC分类号： G11C7/1018
摘要： There are provided a synchronous RAM controlling device and method for controlling a synchronous RAM in order to access data when a burst length of a memory access is full page regardless of whether a termination access method or a wrap-around access method is used. In the synchronous RAM controlling device, an OR gate performs an OR operation on a burst stop signal for stopping input/output of data in the synchronous RAM responsive to an externally received input/output operation command signal. A counter is reset in response to the OR-operation result and counts the cycles of an external system clock signal. A burst sensor senses completion of a burst operation according to a burst length signal which is externally received and represents a burst length of at least 1 and outputs the sensed result as the burst stop signal. A control signal is input to the burst sensor which causes the burst sensor to operate the memory in one of termination or wrap-around access methods. A controller outputs the control signal, where the value of the control signal indicates termination access method when a fuse of the controller is not cut and either no logic level or a high logic level are input to an input pad of the controller. When the fuse is cut or a logic low level is input to the input pad, then the control signal output by the controller will indicate wrap-around access method.
摘要翻译：提供了一种用于控制同步RAM的同步RAM控制装置和方法，以便当存储器访问的突发长度是全页时访问数据，而不管终端访问方法还是环绕访问方法是否被使用。在同步RAM控制装置中，OR门响应于外部接收的输入/输出操作命令信号，对突发停止信号执行OR操作，以停止同步RAM中的数据的输入/输出。计数器响应于或运算结果而复位，并对外部系统时钟信号的周期进行计数。突发传感器根据外部接收的突发长度信号来感测突发操作的完成，并且表示至少为1的突发长度，并将感测结果输出为突发停止信号。控制信号被输入到突发传感器，其使得突发传感器以终止或环绕访问方法之一来操作存储器。控制器输出控制信号，其中控制信号的值表示当控制器的熔丝没有被切断并且没有逻辑电平或高逻辑电平被输入到控制器的输入焊盘时的终止访问方法。当熔断器被切断或逻辑低电平输入到输入焊盘时，控制器输出的控制信号将指示环绕存取方式。

3. 发明授权

US5677877A Integrated circuit chips with multiplexed input/output pads and methods of operating same 失效
标题翻译：具有复用输入/输出焊盘的集成电路芯片及其操作方法
公开(公告)号：US5677877A
公开(公告)日：1997-10-14
申请号：US651375
申请日：1996-05-22
申请人： Sei-Seung Yoon , Tae-Seong Jang
发明人： Sei-Seung Yoon , Tae-Seong Jang
IPC分类号： G11C11/41 , G11C5/06 , G11C11/407 , G11C29/00 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00 , G11C8/00
CPC分类号： G11C29/808 , G11C29/84 , G11C5/066
摘要： Integrated circuit chips with multiplexed input/output pads include means for expanding the functional and diagnostic capability of the circuit by increasing the effective number of input/output pads connected thereto so that more information can be provided to and from the chip. In particular, multiplexing means preferably provides the capability of accessing any one of a plurality of signal lines in the circuit from each input/output pad. This expanded capability is preferably achieved using one or more selection control signals which can be generated internally or externally to a chip containing the integrated circuit. An integrated circuit memory device, for example, preferably comprises a semiconductor substrate, a memory circuit in the substrate, a plurality of input/output pads and means, coupled to signal lines in the memory circuit, for multiplexing the plurality of input/output pads to the signal lines by electrically connecting respective ones of the signal lines to the input/output pads in response to a first select signal and electrically connecting respective others of the signal lines to the input/output pads in response to a second select signal. Because each pad on a chip can be connected to one or more signal lines, the memory circuit has a greater number of effective pads which means that a fewer number of pads on a small memory circuit chip can provide essentially the same input/output capability as a greater number of pads on a larger chip.
摘要翻译：具有复用输入/输出焊盘的集成电路芯片包括通过增加连接到其上的输入/输出焊盘的有效数量来扩展电路的功能和诊断能力的装置，以便可以向芯片提供更多的信息。具体地，复用装置优选地提供从每个输入/输出焊盘访问电路中的多条信号线中的任何一条的能力。该扩展能力优选地使用可以在包含集成电路的芯片的内部或外部产生的一个或多个选择控制信号来实现。例如，集成电路存储器件优选地包括半导体衬底，衬底中的存储器电路，耦合到存储器电路中的信号线的多个输入/输出焊盘和装置，用于多路复用多个输入/输出焊盘通过响应于第一选择信号将相应的信号线电连接到输入/输出焊盘并且响应于第二选择信号将各个信号线电连接到输入/输出焊盘而将信号线连接到信号线。因为芯片上的每个焊盘可以连接到一个或多个信号线，所以存储器电路具有更多数量的有效焊盘，这意味着小存储器电路芯片上较少数量的焊盘可以提供基本相同的输入/输出能力更大数量的焊盘在更大的芯片上。

4. 发明授权

US5579268A Semiconductor memory device capable of driving word lines at high speed 失效
标题翻译：能够高速驱动字线的半导体存储器件
公开(公告)号：US5579268A
公开(公告)日：1996-11-26
申请号：US580885
申请日：1995-12-29
申请人： Dong-Il Seo , Tae-Seong Jang
发明人： Dong-Il Seo , Tae-Seong Jang
IPC分类号： G11C8/08 , G11C29/00 , G11C11/40
CPC分类号： G11C29/844 , G11C8/08 , G11C29/781
摘要： A semiconductor memory device for driving word lines at high speed has a word line signal generating circuit for receiving a predecoded signal of a row address, and power source supply circuit for supplying the output signal of the word line signal generating circuit to a word line as source power. The device includes a normal word line decoder for receiving the predecoded signal and the output signal of the power source supplying circuit, respectively and for selecting a normal word line; a spare word line decoder for receiving the predecoded signal and the output signal of the power source supply circuit, respectively and for selecting a spare word line; and a redundancy enabling circuit connected to the spare word line decoder and the normal word line decoder for determining whether the normal word line is selected.
摘要翻译：用于高速驱动字线的半导体存储器件具有用于接收行地址的预解码信号的字线信号发生电路和用于将字线信号发生电路的输出信号提供给字线的电源供应电路，源功率该装置包括用于分别接收预解码信号和电源供给电路的输出信号的正常字线解码器，用于选择正常字线; 用于分别接收所述预解码信号和所述电源供给电路的输出信号的备用字线解码器，用于选择备用字线; 以及连接到备用字线解码器和通常字线解码器的冗余使能电路，用于确定是否选择了正常字线。

5. 发明授权

US09588840B2 Memory devices that perform masked write operations and methods of operating the same 有权
标题翻译：执行屏蔽写操作的内存设备及其操作方法
公开(公告)号：US09588840B2
公开(公告)日：2017-03-07
申请号：US14225686
申请日：2014-03-26
申请人： Hoi-ju Chung , Chul-sung Park , Tae-young Oh , Jang-woo Ryu , Chan-yong Lee , Tae-seong Jang , Gong-heum Han
发明人： Hoi-ju Chung , Chul-sung Park , Tae-young Oh , Jang-woo Ryu , Chan-yong Lee , Tae-seong Jang , Gong-heum Han
IPC分类号： G06F11/10 , G06F11/32
CPC分类号： G06F11/1048 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G06F11/1076
摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.
摘要翻译：一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

6. 发明授权

US09036439B2 Semiconductor memory device having improved refresh characteristics 有权
标题翻译：具有改善的刷新特性的半导体存储器件
公开(公告)号：US09036439B2
公开(公告)日：2015-05-19
申请号：US13548484
申请日：2012-07-13
申请人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
发明人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
IPC分类号： G11C29/08 , G11C7/00 , G11C29/50 , G11C11/406 , G11C5/04 , G11C11/40
CPC分类号： G11C29/50016 , G11C5/04 , G11C11/40 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
摘要翻译：具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

7. 发明申请

US20140317470A1 MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME 有权
标题翻译：执行掩蔽写操作的记忆设备及其操作方法
公开(公告)号：US20140317470A1
公开(公告)日：2014-10-23
申请号：US14225686
申请日：2014-03-26
申请人： Hoi-ju CHUNG , Chul-sung PARK , Tae-young OH , Jang-woo RYU , Chan-yong LEE , Tae-seong JANG , Gong-heum HAN
发明人： Hoi-ju CHUNG , Chul-sung PARK , Tae-young OH , Jang-woo RYU , Chan-yong LEE , Tae-seong JANG , Gong-heum HAN
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G06F11/1076
摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.
摘要翻译：一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

8. 发明申请

US20070036019A1 Circuit for selecting a power supply voltage and semiconductor device having the same 失效
标题翻译：用于选择电源电压的电路和具有该电源电压的半导体器件
公开(公告)号：US20070036019A1
公开(公告)日：2007-02-15
申请号：US11500346
申请日：2006-08-08
申请人： Tae-Seong Jang
发明人： Tae-Seong Jang
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C29/02 , G11C29/021 , G11C29/1201
摘要： A semiconductor memory device capable of reducing the number of pads is provided. The semiconductor memory device may include a pad, a power supply voltage generating circuit and a voltage selection circuit. The power supply voltage generating circuit may generate one or more power supply voltages, which may be used in a semiconductor device. The voltage selection circuit may select one of the power supply voltages in response to test mode signals to provide the selected power supply voltage to the pad. The voltage selection circuit may include a voltage level regulating circuit to convert voltage levels of the test mode signals to generate gate control signals and metal-oxide semiconductor (MOS) transistors connected to the power supply voltages, respectively. The MOS transistors may be selectively turned on in response to the gate control signals to provide the selected power supply voltage to the pad.
摘要翻译：提供了能够减少焊盘数量的半导体存储器件。半导体存储器件可以包括焊盘，电源电压产生电路和电压选择电路。电源电压发生电路可以产生可用于半导体器件中的一个或多个电源电压。电压选择电路可以响应于测试模式信号选择电源电压之一，以将所选择的电源电压提供给焊盘。电压选择电路可以包括电压电平调节电路，以分别转换测试模式信号的电压电平以产生连接到电源电压的栅极控制信号和金属氧化物半导体（MOS）晶体管。可以响应于栅极控制信号选择性地导通MOS晶体管，以向焊盘提供所选择的电源电压。

9. 发明授权

US06514293B1 Prosthetic foot 失效
标题翻译：假脚
公开(公告)号：US06514293B1
公开(公告)日：2003-02-04
申请号：US09693943
申请日：2000-10-23
申请人： Tae Seong Jang , Dong Hee Lee , Jung Ju Lee , Yong San Yoon
发明人： Tae Seong Jang , Dong Hee Lee , Jung Ju Lee , Yong San Yoon
IPC分类号： A61F266
CPC分类号： A61F2/66 , A61F2002/5003 , A61F2002/5055 , A61F2002/665 , A61F2002/6657
摘要： Disclosed herewith is a prosthetic foot. The prosthetic foot is to be connected to a pylon that is utilized for the substitution of the shinbone of an amputee. The prosthetic foot includes an ankle portion to be secured to the pylon. A plurality of curved portions are extended from one end of the ankle portion. A sole portion is extended from one end of the curved portions. The ankle portion, the curved portions and the sole portion form a single integrated plate spring structure.
摘要翻译：此处公开的是假脚。假脚连接到用于替代被截肢者的胫骨的吊架。假脚包括固定到塔架的脚踝部分。多个弯曲部从踝部的一端延伸。鞋底部分从弯曲部分的一端延伸。脚踝部分，弯曲部分和鞋底部分形成单个集成板簧结构。

10. 发明授权

US6031786A Operation control circuits and methods for integrated circuit memory devices 有权
标题翻译：用于集成电路存储器件的操作控制电路和方法
公开(公告)号：US6031786A
公开(公告)日：2000-02-29
申请号：US134807
申请日：1998-08-14
申请人： Tae-seong Jang , Sung-keun Lee
发明人： Tae-seong Jang , Sung-keun Lee
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , G11C11/401 , G11C29/12 , G11C13/00
CPC分类号： G11C7/22 , G11C8/18
摘要： An operation control circuit of an integrated circuit memory device operates in a synchronous mode according to an internal clock signal. An internal clock controller generates an internal clock enable signal in response to a mode command. An internal clock generator generates the internal clock signal based on the internal clock enable signal and an external clock. In particular, an internal clock controller generates an internal clock enable signal in response to a mode command. Accordingly, the integrated circuit memory device may be free of a clock enable pin.
摘要翻译：集成电路存储器件的操作控制电路根据内部时钟信号在同步模式下工作。内部时钟控制器响应于模式命令产生内部时钟使能信号。内部时钟发生器根据内部时钟使能信号和外部时钟产生内部时钟信号。特别地，内部时钟控制器响应于模式命令产生内部时钟使能信号。因此，集成电路存储器件可以没有时钟使能引脚。

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