专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09588840B2 Memory devices that perform masked write operations and methods of operating the same 有权
标题翻译：执行屏蔽写操作的内存设备及其操作方法
公开(公告)号：US09588840B2
公开(公告)日：2017-03-07
申请号：US14225686
申请日：2014-03-26
申请人： Hoi-ju Chung , Chul-sung Park , Tae-young Oh , Jang-woo Ryu , Chan-yong Lee , Tae-seong Jang , Gong-heum Han
发明人： Hoi-ju Chung , Chul-sung Park , Tae-young Oh , Jang-woo Ryu , Chan-yong Lee , Tae-seong Jang , Gong-heum Han
IPC分类号： G06F11/10 , G06F11/32
CPC分类号： G06F11/1048 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G06F11/1076
摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.
摘要翻译：一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

2. 发明申请

US20140317470A1 MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME 有权
标题翻译：执行掩蔽写操作的记忆设备及其操作方法
公开(公告)号：US20140317470A1
公开(公告)日：2014-10-23
申请号：US14225686
申请日：2014-03-26
申请人： Hoi-ju CHUNG , Chul-sung PARK , Tae-young OH , Jang-woo RYU , Chan-yong LEE , Tae-seong JANG , Gong-heum HAN
发明人： Hoi-ju CHUNG , Chul-sung PARK , Tae-young OH , Jang-woo RYU , Chan-yong LEE , Tae-seong JANG , Gong-heum HAN
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/1008 , G06F11/1068 , G06F11/1072 , G06F11/1076
摘要： A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells.
摘要翻译：一种操作存储器件的方法包括：响应于接收到的屏蔽写入命令产生内部读取命令，内部读取命令被生成（i）在与所接收的被屏蔽写入命令相关联的写入延迟期间，（ii）之后在多个屏蔽写入数据位之间接收第一位掩蔽写入数据，以及（iii）与用与掩蔽写入命令对应的地址信号接收的时钟信号的上升沿或下降沿同步; 响应于所述内部读取命令，读取存储在多个存储器单元中的多个位数据，所述多个存储器单元对应于所述地址信号; 以及响应于内部写入命令，在所述多个存储器单元中存储所述多个掩码写入数据位。

3. 发明授权

US08576644B2 Memory devices having controllers that divide command signals into two signals and systems including such memory devices 有权
标题翻译：具有将命令信号分成两个信号的控制器的存储器件和包括这种存储器件的系统
公开(公告)号：US08576644B2
公开(公告)日：2013-11-05
申请号：US13348672
申请日：2012-01-12
申请人： Seong Hyun Jeon , Hoi Ju Chung , Jung Sunwoo
发明人： Seong Hyun Jeon , Hoi Ju Chung , Jung Sunwoo
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G06F11/1048 , G06F2213/0038 , G11C7/109 , G11C7/22 , G11C2029/0411
摘要： A memory device using error correcting code and a system including the same are provided. The memory device includes a memory cell array including a plurality of bit lines and a plurality of memory cells; an access block for accessing the memory cell array; and a controller block for receiving a first operation command signal, dividing the first operation command signal into at least two paths pulse signals corresponding to at least two paths, based on a pre-determined criterion, and then supplying the at least two path pulse signals to the access block. The access block operates based on an output signal of the controller block.
摘要翻译：提供了使用纠错码的存储装置和包括该存储装置的系统。存储器件包括一个包括多个位线和多个存储单元的存储单元阵列; 访问所述存储单元阵列的访问块; 以及控制器块，用于接收第一操作命令信号，基于预定准则将第一操作命令信号划分为与至少两个路径相对应的至少两个路径脉冲信号，然后提供至少两个路径脉冲信号到访问块。访问块基于控制器块的输出信号进行操作。

4. 发明申请

US20160042809A1 SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权
标题翻译：半导体存储器件和存储器系统，包括它们
公开(公告)号：US20160042809A1
公开(公告)日：2016-02-11
申请号：US14798634
申请日：2015-07-14
申请人： Young-Il KIM , Hoi-ju CHUNG
发明人： Young-Il KIM , Hoi-ju CHUNG
IPC分类号： G11C29/42 , G11C29/44 , G11C29/36
CPC分类号： G11C29/42 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C2029/0411
摘要： A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.
摘要翻译：半导体存储器件包括存储单元阵列，输入/输出（I / O）选通电路，错误判定电路和错误校验（ECC）电路。 I / O门控电路读取测试模式数据，以便在测试模式下提供测试结果数据，并以正常模式读取码字。错误判定电路基于测试图形数据和测试结果数据，确定第一单元在测试结果数据中的错误的可校正性，并且在测试模式中提供指示第一确定结果的第一错误种类信号。 ECC电路对包括主数据和基于主数据生成的奇偶校验数据的码字进行解码，由第二单元确定码字中的错误的可校正性，并在正常模式下提供指示第二确定结果的第二错误种类信号。主数据包括多个单位数据。

5. 发明申请

US20140317469A1 MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION 有权
标题翻译：用于执行错误修正代码操作和冗余维修操作的存储器件
公开(公告)号：US20140317469A1
公开(公告)日：2014-10-23
申请号：US14208795
申请日：2014-03-13
申请人： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
发明人： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
IPC分类号： G06F11/10 , G11C29/10
CPC分类号： G06F11/1068 , G06F3/064 , G06F3/0679 , G06F11/1052 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/808 , G11C29/848 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
摘要： Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
摘要翻译：提供了执行ECC操作和冗余修复操作的存储器件和存储器模块。存储器件通过使用纠错码（ECC）操作来修复由于“故障”单元而导致的单位错误，并且当“失败”单元不可修复时，通过使用冗余修复操作来修复“失败”单元通过ECC操作。冗余修复操作包括数据线修复和块修复。 ECC操作可以改变对应于包括“失败”单元的每单位存储器单元的数据的码字，并且还可以改变关于改变的码字的奇偶校验位的大小。

6. 发明申请

US20110267876A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20110267876A1
公开(公告)日：2011-11-03
申请号：US13085453
申请日：2011-04-12
申请人： Byung-Jun MIN , Hoi-Ju CHUNG
发明人： Byung-Jun MIN , Hoi-Ju CHUNG
IPC分类号： G11C11/00 , G11C29/04
CPC分类号： G11C8/12 , G11C13/0004 , G11C29/80 , G11C29/846
摘要： A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.
摘要翻译：采用可变电阻元件的非易失性存储器件包括：具有多个存储单元的存储单元阵列; 第一电路块，设置在所述存储单元阵列的一侧，并对所述存储单元执行第一操作; 第二电路块，设置在存储单元阵列的另一侧，并对存储单元执行第二操作，其中第二操作与第一操作不同; 以及与第一电路块相比更靠近第二电路块设置的冗余块，并且将多个存储单元中的修复存储单元的修复地址与输入地址进行比较，然后生成冗余控制信号，并且将冗余控制信号提供给第一电路块和第二电路块。

7. 发明申请

US20110261615A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件，具有该半导体器件的半导体器件，以及用于操作半导体器件的方法
公开(公告)号：US20110261615A1
公开(公告)日：2011-10-27
申请号：US13073021
申请日：2011-03-28
申请人： Joon-Yong CHOI , Hoi Ju CHUNG
发明人： Joon-Yong CHOI , Hoi Ju CHUNG
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0076 , G11C2013/0085 , G11C2213/72
摘要： A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.
摘要翻译：半导体器件包括相变存储单元和存取电路。存取电路产生多个按比特比较信号，指示不同比较事件的各个写和读位组。然后根据用于每个比较事件的激活的比较信号的数量，以及根据设定的电流脉冲宽度和复位电流脉冲宽度的比率将写入数据的至少一部分写入相变存储器单元应用于相变存储器单元。

8. 发明申请

US20160124784A1 SEMICONDUCTOR MEMORY DEVICES INCLUDING ERROR CORRECTION CIRCUITS AND METHODS OF OPERATING THE SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：包括误差校正电路的半导体存储器件及其操作半导体存储器件的方法
公开(公告)号：US20160124784A1
公开(公告)日：2016-05-05
申请号：US14992472
申请日：2016-01-11
申请人： Hoi-ju CHUNG , Su-a KIM , Mu-jin SEO , Hak-soo YU , Jae-youn YOUN , Hyo-jin CHOI
发明人： Hoi-ju CHUNG , Su-a KIM , Mu-jin SEO , Hak-soo YU , Jae-youn YOUN , Hyo-jin CHOI
IPC分类号： G06F11/07 , G11C11/409 , G06F11/10 , G11C29/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F11/073 , G06F11/076 , G06F11/079 , G06F11/0793 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G11C11/409 , G11C29/52 , G11C29/783
摘要： A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.
摘要翻译：存储器控制器包括：控制器输入/输出电路，被配置为输出第一命令以读取第一数据，并输出第二命令以读取第一数据的纠错部分。存储装置包括：误差检测器，数据存储电路和纠错电路。错误检测器被配置为响应于第一命令来检测从存储器单元读取的数据中的错误位数。如果检测到的错误比特数大于或等于第一阈值，则数据存储电路被配置为存储读取数据。误差校正电路被配置为校正存储的数据。

9. 发明申请

US20160055056A1 MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION 有权
标题翻译：具有错误通知功能的存储器
公开(公告)号：US20160055056A1
公开(公告)日：2016-02-25
申请号：US14729656
申请日：2015-06-03
申请人： Jong-Pil SON , Chul-Woo PARK , Seong-Jin JANG , Hoi-Ju CHUNG , Sang-Uhn CHA
发明人： Jong-Pil SON , Chul-Woo PARK , Seong-Jin JANG , Hoi-Ju CHUNG , Sang-Uhn CHA
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1008 , G06F11/1004 , G06F11/1024 , G06F11/1068 , G06F11/1666 , G11C2029/0411
摘要： A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.
摘要翻译：具有错误通知功能的存储装置包括通过对多个存储单元的数据执行ECC操作来检测和校正错误位的纠错码（ECC）引擎，以及错误通知电路，配置为根据 ECC操作。 ECC引擎输出与通过ECC操作校正的特定地址相对应的错误位对应的错误信息。当特定地址与现有一个或多个故障地址中的任一个不同时，错误通知电路可以输出错误信号。

10. 发明授权

US08848465B2 Memory devices including selective RWW and RMW decoding 有权
标题翻译：存储器件包括选择性RWW和RMW解码
公开(公告)号：US08848465B2
公开(公告)日：2014-09-30
申请号：US13532911
申请日：2012-06-26
申请人： Seo-Hee Kim , Seong-Hyun Jeon , Hoi-Ju Chung , Sung-Hoon Kim
发明人： Seo-Hee Kim , Seong-Hyun Jeon , Hoi-Ju Chung , Sung-Hoon Kim
IPC分类号： G11C7/00 , G11C7/10 , G11C7/02
CPC分类号： G11C7/02 , G11C7/1006 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0042 , G11C2213/72
摘要： A nonvolatile memory device is provided, which includes a memory core including a plurality of nonvolatile memory cells, a first read circuit that reads a first codeword from the memory core during a Read While Write (RWW) operation, a second read circuit that reads a second codeword from the memory core during a Read Modification Write (RMW) operation, and a common decoder that is shared by the first read circuit and the second read circuit and selectively decodes the first codeword or the second codeword.
摘要翻译：提供了一种非易失性存储器件，其包括包括多个非易失性存储器单元的存储器核心，在读写时（RWW）操作期间从存储器核心读取第一代码字的第一读取电路，读取第一读取电路在读取修改写入（RMW）操作期间来自存储器核心的第二码字以及由第一读取电路和第二读取电路共享的公共解码器，并且选择性地解码第一码字或第二码字。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式