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1. 发明授权

US5638006A Method and apparatus for wafer level prediction of thin oxide reliability using differentially sized gate-like antennae 失效
标题翻译：使用差分尺寸的栅状天线进行晶片级预测薄氧化物可靠性的方法和装置
公开(公告)号：US5638006A
公开(公告)日：1997-06-10
申请号：US453322
申请日：1995-05-30
申请人： Subhash R. Nariani , Calvin T. Gabriel
发明人： Subhash R. Nariani , Calvin T. Gabriel
IPC分类号： G01R31/28 , H01L21/66 , G01R31/26
CPC分类号： G01R31/2856 , G01R31/2831 , H01L22/12 , H01L22/14
摘要： An IC wafer containing thin oxide is fabricated to include at least two differentially-sized plate areas that may be upper plates of capacitors, or gates of associated MOS transistors. Before testing, the thin gate oxide underlying these plate areas is intentionally stressed by applying a stress current between these plates and the substrate. The stress current magnitude is scaled to the plate area such that each plate sees a substantially constant current density. Because weak oxide defects occur somewhat uniformly throughout the thin oxide, a larger plate or gate will overlie more weak oxide defects than will a plate or gate. If wafer test leakage current between the larger plate or gate and substrate exceeds leakage current between the smaller plate or gate and substrate, weak oxide is indicated because the defect is area dependent. By contrast, charge-induced damage is substantially independent of the areas of the plates or gates, due to the scaling of the stress-inducing currents. Thus, if test leakage current on the wafer is substantially the same for the large and small sized plates or gates, charge-damaged oxide is indicated because the damage is not area dependent. If desired, defects in the thin (gate) oxide may be identified by examining the characteristics of the test MOS devices. The gate-like plates (and if present associated MOS devices) are sufficiently small to be fabricated within scribe lines of the wafer to be tested.
摘要翻译：包含薄氧化物的IC晶片被制造成包括至少两个不同尺寸的板区域，其可以是电容器的上板，或者相关联的MOS晶体管的栅极。在测试之前，通过在这些板和衬底之间施加应力电流来有意地强调这些板区域下面的薄栅极氧化物。应力电流大小被缩放到板区域，使得每个板看到基本上恒定的电流密度。由于弱的氧化物缺陷在整个薄氧化物中有一些均匀的发生，所以与板或栅极相比，较大的板或栅极将覆盖更多的弱氧化物缺陷。如果较大的板或栅极和衬底之间的晶片测试漏电流超过较小的板或栅极和衬底之间的漏电流，则表示弱氧化物，因为缺陷是面积依赖的。相反，由于应力诱导电流的缩放，电荷诱导的损伤基本上与板或栅极的区域无关。因此，如果大型和小型板或栅极上的晶片上的测试漏电流基本相同，则表示电荷损坏的氧化物，因为损坏不是区域依赖的。如果需要，可以通过检查测试MOS器件的特性来识别薄（栅极）氧化物中的缺陷。栅极板（以及如果存在相关联的MOS器件）足够小以在要测试的晶片的划线内制造。

2. 发明授权

US5470775A Method of forming a polysilicon-on-silicide capacitor 失效
标题翻译：形成硅化硅电容器的方法
公开(公告)号：US5470775A
公开(公告)日：1995-11-28
申请号：US149085
申请日：1993-11-09
申请人： Subhash R. Nariani
发明人： Subhash R. Nariani
IPC分类号： H01L21/02 , H01L27/00 , H01L21/70
CPC分类号： H01L28/20 , H01L28/40
摘要： A method produces a capacitor. On a substrate, a first polysilicon layer is formed over an insulating region. A metal-silicide layer is formed on top of the first polysilicon layer. A dielectric layer is formed on top of the metal-silicide layer. A second polysilicon layer is formed on top of the dielectric layer. The second polysilicon layer and the dielectric layer are etched to form a top electrode and dielectric region. The metal-silicide layer and the first polysilicon layer are etched to form a bottom electrode.
摘要翻译：一种方法产生电容器。在基板上，在绝缘区域上形成第一多晶硅层。在第一多晶硅层的顶部上形成金属硅化物层。介电层形成在金属硅化物层的顶部。第二多晶硅层形成在电介质层的顶部。蚀刻第二多晶硅层和电介质层以形成顶部电极和电介质区域。蚀刻金属硅化物层和第一多晶硅层以形成底部电极。

3. 发明授权

US5374833A Structure for suppression of field inversion caused by charge build-up in the dielectric 失效
标题翻译：用于抑制由电介质中的电荷积聚引起的场反转的结构
公开(公告)号：US5374833A
公开(公告)日：1994-12-20
申请号：US775085
申请日：1991-10-11
申请人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
发明人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/314 , H01L21/316 , H01L23/29 , H01L23/532 , H01L27/115 , H02L45/00
CPC分类号： H01L23/291 , H01L21/314 , H01L23/298 , H01L23/5329 , H01L27/115 , H01L2924/0002 , Y10S438/91 , Y10S438/958
摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
摘要翻译：本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

4. 发明授权

US5328865A Method for making cusp-free anti-fuse structures 失效
标题翻译：制造无尖锐反熔丝结构的方法
公开(公告)号：US5328865A
公开(公告)日：1994-07-12
申请号：US11084
申请日：1993-01-29
申请人： William J. Boardman , David P. Chan , Kuang-Yeh Chang , Calvin T. Gabriel , Vivek Jain , Subhash R. Nariani
发明人： William J. Boardman , David P. Chan , Kuang-Yeh Chang , Calvin T. Gabriel , Vivek Jain , Subhash R. Nariani
IPC分类号： H01L21/768 , H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L21/76888 , H01L2924/0002
摘要： A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.
摘要翻译：一种制造抗熔丝结构的方法，其特征在于形成导电基层的步骤; 在基层上形成抗熔丝层; 图案化抗熔丝层以形成抗熔丝岛; 在反熔丝岛上形成绝缘层; 形成通过所述绝缘层到所述反熔丝岛的通孔; 在所述绝缘层上并在所述通孔内形成导电连接层; 以及图案化所述导电连接层以形成与所述反熔丝岛的导电接触。优选地，抗熔丝岛包括非晶硅，其可任选地被钛 - 钨合金的薄层覆盖。

5. 发明授权

US5492865A Method of making structure for suppression of field inversion caused by charge build-up in the dielectric 失效
标题翻译：制造电介质中电荷积聚引起的场反转抑制结构的方法
公开(公告)号：US5492865A
公开(公告)日：1996-02-20
申请号：US314425
申请日：1994-09-28
申请人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
发明人： Subhash R. Nariani , Vivek Jain , Dipankar Pramanik , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/314 , H01L21/316 , H01L23/29 , H01L23/532 , H01L27/115 , H01L21/44 , H01L21/48
CPC分类号： H01L23/291 , H01L21/314 , H01L23/298 , H01L23/5329 , H01L27/115 , H01L2924/0002 , Y10S438/91 , Y10S438/958
摘要： The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
摘要翻译：本发明涉及一种集成电路，其包括用于中和在制造期间在各种介电层中发生的电荷的一个或多个非晶硅层。非晶硅层包括悬挂硅键，其中和电荷，否则将导致隔离击穿，损害集成电路性能并增加制造成本。

6. 再颁专利

USRE36893E Anti-fuse structure for reducing contamination of the anti-fuse material 失效
标题翻译：防熔丝结构，可减少反熔丝材料的污染
公开(公告)号：USRE36893E
公开(公告)日：2000-10-03
申请号：US795098
申请日：1997-02-06
申请人： Dipankar Pramanik , Subhash R. Nariani
发明人： Dipankar Pramanik , Subhash R. Nariani
IPC分类号： H01L23/525 , H01L29/00 , H01L23/48 , H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug including a conductive barrier material such as TiN or TiW to contact the anti-fuse material and overlie the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separaged from the anti-fuse layer by at least one-half the depth of the via hole. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
摘要翻译：根据本发明形成的抗熔丝结构包括导电层基底。一层抗熔丝材料覆盖在导电基层上。在抗熔丝层的顶部是绝缘层，其中在反熔丝层上形成通孔。通孔的横向尺寸小于约0.8微米。在通孔中设置有导电非Al插塞，其包括诸如TiN或TiW的导电阻挡材料以接触抗熔丝材料并覆盖在绝缘层上。钨被有效地用作非铝插头。导电层形成在插塞上方，并且与抗熔丝层分开至少通孔深度的二分之一。然后通过施加编程电压可编程结构，并通过施加低于编程电压的感测电压来读取结构。

7. 发明授权

US6015732A Dual gate oxide process with increased reliability 失效
标题翻译：双栅氧化工艺具有更高的可靠性
公开(公告)号：US6015732A
公开(公告)日：2000-01-18
申请号：US709479
申请日：1996-09-06
申请人： Jon Roderick Williamson , Subhash R. Nariani
发明人： Jon Roderick Williamson , Subhash R. Nariani
IPC分类号： H01L21/8234 , H01L21/8247 , H01L27/088 , H01L21/8242
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/088 , H01L27/11539
摘要： Within a dual gate oxide process, gate oxide is formed within regions on a substrate. Gate material, such as polysilicon, is placed over a first region. The gate material extends over field oxide surrounding the first region. Gate oxide within a second region is stripped. The gate material over the first region prevents gate oxide within the first region from being stripped. A new layer of gate oxide is formed within the second region. A first transistor gate is formed within the second region. The gate material which is over the first region is etched to form a second transistor gate.
摘要翻译：在双栅极氧化物工艺中，栅极氧化物形成在衬底上的区域内。诸如多晶硅的栅极材料放置在第一区域上。栅极材料在围绕第一区域的场氧化物上延伸。剥离第二区域内的栅极氧化物。第一区域上的栅极材料防止第一区域内的栅极氧化物被剥离。在第二区域内形成新的栅极氧化层。第一晶体管栅极形成在第二区域内。在第一区域之上的栅极材料被蚀刻以形成第二晶体管栅极。

8. 发明授权

US5602056A Method for forming reliable MOS devices using silicon rich plasma oxide film 失效
标题翻译：使用富硅等离子体氧化膜形成可靠的MOS器件的方法
公开(公告)号：US5602056A
公开(公告)日：1997-02-11
申请号：US434528
申请日：1995-05-04
申请人： Vivek Jain , Dipankar Pramanik , Subhash R. Nariani , Kuang-Yeh Chang
发明人： Vivek Jain , Dipankar Pramanik , Subhash R. Nariani , Kuang-Yeh Chang
IPC分类号： H01L21/314 , H01L21/316 , H01L23/29 , H01L23/532 , H01L27/115 , H01L21/44
CPC分类号： H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/02282 , H01L21/314 , H01L21/31612 , H01L23/291 , H01L23/298 , H01L23/5329 , H01L27/115 , H01L2924/0002
摘要： The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.
摘要翻译：本发明涉及用于制造具有多层金属化的MOS器件的MOS器件和方法。根据优选实施例，内部钝化用于抑制来自内部源的器件劣化。用于制造这种器件的优选器件和方法包括形成富含硅的一个或多个氧化物层以提供这种内部钝化并改善热载流子寿命。用于制造具有多层金属化的MOS器件的优选方法包括改变PECVD氧化物膜的组成，并且在一些实施例中改变这种氧化物的位置和厚度。在示例性优选实施例中，通过将组合物改变为富含氧化物的氧化物来修饰PECVD氧化物层。

9. 发明授权

US5573970A Method for reducing contamination of anti-fuse material in an anti-fuse structure 失效
标题翻译：减少反熔丝结构中抗熔丝材料污染的方法
公开(公告)号：US5573970A
公开(公告)日：1996-11-12
申请号：US477311
申请日：1995-06-06
申请人： Dipankar Pramanik , Subhash R. Nariani
发明人： Dipankar Pramanik , Subhash R. Nariani
IPC分类号： H01L23/525 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5252 , H01L2924/0002 , Y10S148/055
摘要： An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
摘要翻译：根据本发明形成的抗熔丝结构包括导电层基底。一层抗熔丝材料覆盖在导电基层上。在抗熔丝层的顶部是绝缘层，其中在反熔丝层上形成通孔。通孔的横向尺寸小于约0.8微米。在通孔中设置有导电性非铝塞，其覆盖与导电阻挡材料（例如TiN或TiW）接触反熔丝材料并覆盖绝缘层的层。钨被有效地用作非铝插头。导电层形成在插塞上方，并且通过插头与覆盖抗熔丝层的导电阻挡材料分离。然后通过施加编程电压可编程结构，并通过施加低于编程电压的感测电压来读取结构。

10. 发明授权

US5128279A Charge neutralization using silicon-enriched oxide layer 失效
标题翻译：使用富氧氧化物层进行电荷中和
公开(公告)号：US5128279A
公开(公告)日：1992-07-07
申请号：US776503
申请日：1991-10-11
申请人： Subhash R. Nariani , Dipankar Pramanik
发明人： Subhash R. Nariani , Dipankar Pramanik
IPC分类号： H01L23/29 , H01L23/532 , H01L27/115
CPC分类号： H01L23/291 , H01L23/5329 , H01L27/115 , H01L2924/0002 , Y10S438/958
摘要： Parasitic leakage is minimized in a MOS structure. An integrated circuit wafer comprises conventional MOS elements as applied through a first level metallization. An intermetal dielectric includes three layers, an intermediate organic glass layer used for planarization and upper and lower oxide layers. A second metallization is applied over the dielectric. Passivation includes a lower oxide passivation and an upper nitride passivation. Hydrogen from the nitride passivation migrates into the organic glass and forms positive charges that induce the parasitic leakage. The lower oxide layer in the intermetal dielectric is silicon-enriched to provide dangling bonds which neutralize this charge formation and thus minimize the parasitic leakage.
摘要翻译：在MOS结构中寄生泄漏最小化。集成电路晶片包括通过第一级金属化施加的常规MOS元件。金属间电介质包括三层，用于平坦化的中间有机玻璃层和上部和下部氧化物层。在电介质上施加第二金属化。钝化包括较低的氧化物钝化和上部氮化物钝化。来自氮化物钝化的氢迁移到有机玻璃中并形成诱发寄生泄漏的正电荷。金属间电介质中的低氧化物层是富含硅的，以提供悬挂键，其中和这种电荷形成，从而最小化寄生泄漏。

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