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1. 发明授权

US07994835B2 Duty control circuit and semiconductor device having the same 有权
标题翻译：占空比控制电路和具有相同功能的半导体器件
公开(公告)号：US07994835B2
公开(公告)日：2011-08-09
申请号：US12585680
申请日：2009-09-22
申请人： Kwan-yeob Chae , Su-ho Kim , Won Lee , Sang-hoon Joo , Dharmendra Pandit , Jong-ryun Choi
发明人： Kwan-yeob Chae , Su-ho Kim , Won Lee , Sang-hoon Joo , Dharmendra Pandit , Jong-ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058
摘要： A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.
摘要翻译：一种占空比控制电路，包括连接到第一节点和第二节点的时钟输入单元，时钟输入单元通过第一节点接收输入时钟信号，并将第二节点的电压改变为第一电压电平和第二节点之一响应于输入时钟信号的相应低和高逻辑电平的电压电平，连接到第二节点的转换控制器，所述转换控制器包括由相应控制信号控制的一个或多个开关，所述一个或多个开关提供第一电压电平和第二电压电平响应于控制信号，使得第二节点处的信号的转换速率改变;以及时钟输出单元，时钟输出单元输出具有占空比的输出时钟信号不一样。

2. 发明申请

US20100073059A1 Duty control circuit and semiconductor device having the same 有权
标题翻译：占空比控制电路和具有相同功能的半导体器件
公开(公告)号：US20100073059A1
公开(公告)日：2010-03-25
申请号：US12585680
申请日：2009-09-22
申请人： Kwan-yeob Chae , Su-ho Kim , Won Lee , Sang-hoon Joo , Dharmendra Pandit , Jong-ryun Choi
发明人： Kwan-yeob Chae , Su-ho Kim , Won Lee , Sang-hoon Joo , Dharmendra Pandit , Jong-ryun Choi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058
摘要： A duty control circuit including a clock input unit connected to a first node and a second node, the clock input unit receiving an input clock signal through the first node and changing a voltage of the second node to one of a first voltage level and a second voltage level in response to respective low and high logic levels of the input clock signal, a slew controller connected to the second node, the slew controller including one or more switches controlled by respective control signals, the one or more switches providing one of the first voltage level and the second voltage level to the second node in response to the control signals such that a slew rate of a signal at the second node is varied, and a clock output unit, the clock output unit outputting an output clock signal having a duty that varies.
摘要翻译：一种占空比控制电路，包括连接到第一节点和第二节点的时钟输入单元，时钟输入单元通过第一节点接收输入时钟信号，并将第二节点的电压改变为第一电压电平和第二节点之一响应于输入时钟信号的相应低和高逻辑电平的电压电平，连接到第二节点的转换控制器，所述转换控制器包括由相应控制信号控制的一个或多个开关，所述一个或多个开关提供第一电压电平和第二电压电平响应于控制信号，使得第二节点处的信号的转换速率改变;以及时钟输出单元，时钟输出单元输出具有占空比的输出时钟信号不一样。

3. 发明授权

US07234011B2 Advanced microcontroller bus architecture (AMBA) system with reduced power consumption and method of driving AMBA system 失效
标题翻译：先进的微控制器总线架构（AMBA）系统具有降低的功耗和驱动AMBA系统的方法
公开(公告)号：US07234011B2
公开(公告)日：2007-06-19
申请号：US10993885
申请日：2004-11-19
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： G06F13/00 , G06F15/00
CPC分类号： G06F13/405 , Y02D10/14 , Y02D10/151
摘要： In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can be reduced in a bus architecture such as an advanced high-performance system bus (AHB).
摘要翻译：在具有降低的功耗的先进的微控制器总线架构（AMBA）系统中，仅通过在需要来自其它负载的信号转换的总线信号传送路径上隔离负载来传送总线信号所需的负载时允许发生信号转换，使得在诸如高级高性能系统总线（AHB）的总线架构中可以降低功耗。

4. 发明申请

US20080197900A1 DELAY LOCKED LOOP FOR CONTROLLING DELAY TIME USING SHIFTER AND ADDER AND CLOCK DELAYING METHOD 有权
标题翻译：延迟锁定环，用于使用移位器和时钟延迟控制延迟时间
公开(公告)号：US20080197900A1
公开(公告)日：2008-08-21
申请号：US12013607
申请日：2008-01-14
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805
摘要： A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value.
摘要翻译：通过使用移位器和加法器来控制延迟时间的延迟锁定环包括主延迟锁定环和从延迟锁定环。主延迟锁定环路输出对应于第一输入时钟信号的一个时钟周期的第一数字值。从属延迟锁定环接收第一数字值并延迟第二输入时钟信号一段时间小于第一输入时钟信号的一个时钟周期。从延迟锁定环包括移位器，操作器和可变延迟电路。移位器移动第一数字值以产生第二数字值。操作者向或从第二数字值增加或减去偏移值以产生第三数字值，其中偏移值根据过程，电压和温度（PVT）而变化。可变延迟电路将第二输入时钟信号延迟与第三数字值对应的时间段。

5. 发明授权

US07254661B2 Methods, circuits, and computer program products for variable bus arbitration 有权
标题翻译：可变总线仲裁的方法，电路和计算机程序产品
公开(公告)号：US07254661B2
公开(公告)日：2007-08-07
申请号：US10921607
申请日：2004-08-19
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： G06F13/36
CPC分类号： G06F13/364
摘要： Arbitration for a communications channel can be provided by scheduling a grant for future access to one of a plurality of requestors to a communications channel shared by the plurality of requestors based on an indication of which of the plurality of requestors is granted access to the communications channel during a current access.
摘要翻译：可以通过基于对多个请求者中的哪一个被许可访问通信信道的指示来调度用于将来访问多个请求者中的一个到多个请求者共享的通信信道的许可的仲裁在当前访问。

6. 发明申请

US20050138253A1 Advanced microcontroller bus architecture (AMBA) system with reduced power consumption and method of driving AMBA system 失效
标题翻译：先进的微控制器总线架构（AMBA）系统具有降低的功耗和驱动AMBA系统的方法
公开(公告)号：US20050138253A1
公开(公告)日：2005-06-23
申请号：US10993885
申请日：2004-11-19
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： G06F3/00 , G06F13/00 , G06F13/14 , G06F13/20 , G06F13/36 , G06F13/38 , G06F13/40 , G06F15/17
CPC分类号： G06F13/405 , Y02D10/14 , Y02D10/151
摘要： In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can be reduced in a bus architecture such as an advanced high-performance system bus (AHB).
摘要翻译：在具有降低的功耗的先进的微控制器总线架构（AMBA）系统中，仅通过在需要来自其它负载的信号转换的总线信号传送路径上隔离负载来传送总线信号所需的负载时允许发生信号转换，使得在诸如高级高性能系统总线（AHB）的总线架构中可以降低功耗。

7. 发明授权

US07701274B2 Delay locked loop for controlling delay time using shifter and adder and clock delaying method 有权
标题翻译：延迟锁定环，用于使用移位器和加法器和时钟延迟方法控制延迟时间
公开(公告)号：US07701274B2
公开(公告)日：2010-04-20
申请号：US12013607
申请日：2008-01-14
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805
摘要： A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value.
摘要翻译：通过使用移位器和加法器来控制延迟时间的延迟锁定环包括主延迟锁定环和从延迟锁定环。主延迟锁定环路输出对应于第一输入时钟信号的一个时钟周期的第一数字值。从属延迟锁定环接收第一数字值并延迟第二输入时钟信号一段时间小于第一输入时钟信号的一个时钟周期。从延迟锁定环包括移位器，操作器和可变延迟电路。移位器移动第一数字值以产生第二数字值。操作者向或从第二数字值增加或减去偏移值以产生第三数字值，其中偏移值根据过程，电压和温度（PVT）而变化。可变延迟电路将第二输入时钟信号延迟与第三数字值对应的时间段。

8. 发明授权

US07073003B2 Programmable fixed priority and round robin arbiter for providing high-speed arbitration and bus control method therein 有权
标题翻译：可编程固定优先级和循环仲裁器，用于在其中提供高速仲裁和总线控制方法
公开(公告)号：US07073003B2
公开(公告)日：2006-07-04
申请号：US10720808
申请日：2003-11-24
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： G06F13/36
CPC分类号： G06F13/364 , Y02D10/14
摘要： In a programmable fixed priority and round-robin arbiter and a bus control method of the same, the arbiter includes, an HPRIF rotating unit, a request-reordering unit, a request-selecting unit, and a grant-reordering unit. In the fixed priority mode or the round-robin mode, the HPRIF rotating unit rotates priority information related to bus masters stored in a predetermined register in a predetermined direction to give the highest priority to a bus master in response to pointer information and outputs changed priority information. When a request signal is received from the bus masters, the request-reordering unit reorders requested priorities of the bus masters to be in accordance with the changed priority information and outputs a request-reordering signal. The request-selecting unit outputs a bus master-selecting signal according to priorities in response to the request-reordering signal. The grant-reordering unit outputs a bus master grant signal to the bus masters according to priorities in response to the bus master-selecting signal.
摘要翻译：在可编程固定优先级和循环仲裁器及其总线控制方法中，仲裁器包括HPRIF旋转单元，请求重新排序单元，请求选择单元和授权重新排序单元。在固定优先模式或循环模式中，HPRIF旋转单元响应于指针信息旋转预定方向上存储在预定寄存器中的与总线主机相关的优先级信息，以向总线主机提供最高优先级，并输出改变的优先级信息。当从总线主机接收到请求信号时，请求重排序单元根据改变的优先级信息重新排列总线主控器的所请求的优先级，并输出请求重排序信号。请求选择单元响应于请求重排序信号，根据优先级输出总线主机选择信号。授权重排单元响应于总线主控选择信号，根据优先级向总线主控器输出总线主控授权信号。

9. 发明授权

US07028121B2 Parameter generating circuit for deciding priority of master blocks and method of generating parameter 有权
标题翻译：用于决定主块优先级的参数产生电路和生成参数的方法
公开(公告)号：US07028121B2
公开(公告)日：2006-04-11
申请号：US10677666
申请日：2003-10-02
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/364
摘要： Provided are a parameter generating circuit and a method of generating a parameter which decides priority of master blocks. An arbitration parameter generating circuit includes a counter, a short term arbitration parameter storage unit, a short term reference time measurement unit, a long term arbitration parameter control unit and a long term reference time measurement unit. The counter receives a request signal generated in order for a master block to occupy a system bus and a grant signal generated in order for an arbitrator to allow the master block to occupy the system bus, up-counts when the request signal is at a first logic level, down-counts when the grant signal is at the first logic level, and is reset in response to a predetermined short term reference time signal. The short term arbitration parameter storage unit receives and stores the counted signal as the short term arbitration parameter until the counter is reset in response to the short term reference time signal. The long term arbitration parameter control unit continuously accumulates the short term arbitration parameter outputted from the short term arbitration parameter storage unit, outputs the accumulated short term arbitration parameter as a long term arbitration parameter, and is reset in response to the long term reference time signal.
摘要翻译：提供了一种参数产生电路和生成决定主块优先级的参数的方法。仲裁参数产生电路包括计数器，短期仲裁参数存储单元，短期参考时间测量单元，长期仲裁参数控制单元和长期参考时间测量单元。计数器接收生成的请求信号，以使主块占用系统总线和生成的授权信号，以便仲裁者允许主控制器占用系统总线，当请求信号处于第一位置时向上计数逻辑电平，当授权信号处于第一逻辑电平时向下计数，并且响应于预定的短期参考时间信号被复位。短期仲裁参数存储单元接收并存储计数信号作为短期仲裁参数，直到计数器响应于短期参考时间信号复位。长期仲裁参数控制单元连续地累积从短期仲裁参数存储单元输出的短期仲裁参数，将累积的短期仲裁参数输出为长期仲裁参数，并根据长期参考时间信号进行复位。

10. 发明申请

US20050060459A1 Methods, circuits, and computer program products for variable bus arbitration 有权
标题翻译：可变总线仲裁的方法，电路和计算机程序产品
公开(公告)号：US20050060459A1
公开(公告)日：2005-03-17
申请号：US10921607
申请日：2004-08-19
申请人： Kwan-yeob Chae
发明人： Kwan-yeob Chae
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00 , G06F13/14 , G06F13/364 , G06F13/38
CPC分类号： G06F13/364
摘要： Arbitration for a communications channel can be provided by scheduling a grant for future access to one of a plurality of requestors to a communications channel shared by the plurality of requestors based on an indication of which of the plurality of requestors is granted access to the communications channel during a current access.
摘要翻译：可以通过基于对多个请求者中的哪一个被许可访问通信信道的指示来调度用于将来访问多个请求者中的一个到多个请求者共享的通信信道的许可的仲裁在当前访问。

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