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1. 发明申请

US20120140685A1 SIMPLIFIED ADAPTIVE FILTER ALGORITHM FOR THE CANCELLATION OF TX-INDUCED EVEN ORDER INTERMODULATION PRODUCTS 审中-公开
标题翻译：简化自适应滤波算法，用于取消TX诱导的即时交互产品
公开(公告)号：US20120140685A1
公开(公告)日：2012-06-07
申请号：US12957612
申请日：2010-12-01
申请人： Christian Lederer , Huemer Mario , Stefan Herzinger , Gernot Hueber , Burkhard Neurauter , Andreas Mayer
发明人： Christian Lederer , Huemer Mario , Stefan Herzinger , Gernot Hueber , Burkhard Neurauter , Andreas Mayer
IPC分类号： H04B3/20 , G06F17/10
CPC分类号： H04L27/3854 , H04L25/03057
摘要： One embodiment of the present invention relates to an adaptive filtering apparatus comprising first and second real valued adaptive filters, respectively configured to receive an adaptive filter input signal based upon a transmission signal in a transmission path. The first real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a first intermodulation noise component (e.g., an in-phase component) in a desired signal and to cancel the estimated noise. The second real valued adaptive filter is configured to operate a real valued adaptive filter algorithm on the input signal to estimate a second intermodulation noise component (e.g., a quadrature phase component) in the desired signal and to cancel the estimated noise. Accordingly, each filter operates a real valued adaptive algorithm to cancel a noise component, thereby removing complex cross terms between the components from the adaptive filtering process.
摘要翻译：本发明的一个实施例涉及一种包括第一和第二实值自适应滤波器的自适应滤波装置，分别被配置为基于传输路径中的传输信号接收自适应滤波器输入信号。第一实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第一互调噪声分量（例如，同相分量）并消除所估计的噪声。第二实值自适应滤波器被配置为在输入信号上操作实值自适应滤波器算法以估计期望信号中的第二互调噪声分量（例如，正交相位分量）并消除所估计的噪声。因此，每个滤波器操作实值自适应算法以消除噪声分量，从而从自适应滤波处理中去除组件之间的复杂交叉项。

2. 发明授权

US07280617B2 Method to compensate for a step DC disturbance in a digital baseband signal in a homodyne radio receiver 有权
标题翻译：补偿零差无线电接收机中的数字基带信号中的步进直流干扰的方法
公开(公告)号：US07280617B2
公开(公告)日：2007-10-09
申请号：US10734707
申请日：2003-12-11
申请人： Michael Cujé , Stefan Eibl , Stefan Herzinger , Martin Krüger , Xiaofeng Wu , Bin Yang
发明人： Michael Cujé , Stefan Eibl , Stefan Herzinger , Martin Krüger , Xiaofeng Wu , Bin Yang
IPC分类号： H04L25/10
CPC分类号： H04B1/30
摘要： In a method to compensate for a step DC disturbance (1) in a baseband signal in a homodyne radio receiver, the time profile of the step DC disturbance within a burst is determined. In order to produce a step-corrected baseband signal, the determined time profile (2) is then calculated from the digitized baseband signal.
摘要翻译：在补偿在零差无线电接收机中的基带信号中的步进DC干扰（1）的方法中，确定突发内的步骤DC干扰的时间曲线。为了产生步进校正的基带信号，则从数字化的基带信号计算确定的时间分布（2）。

3. 发明申请

US20060114071A1 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US20060114071A1
公开(公告)日：2006-06-01
申请号：US11141591
申请日：2005-05-31
申请人： Stefan Herzinger , Gunter Marzinger
发明人： Stefan Herzinger , Gunter Marzinger
IPC分类号： H03L7/00
CPC分类号： H03C3/0983 , H03C3/0941 , H03C3/095 , H03C3/0966 , H03C3/0975 , H03L7/0891 , H03L7/093 , H03L7/18
摘要： A phase locked loop PLL having a forward path and a feedback path is disclosed. A phase detector drives an oscillator in the forward path of the phase locked loop. The feedback path includes a frequency divider that connects the oscillator output to the phase detector. The phase locked loop further includes an integrator-free loop filter configured to control the oscillator. The integrator-free loop filter enables a reduction in the required PLL bandwidth without reducing the signal quality when the PLL is used as a modulator.
摘要翻译：公开了具有正向路径和反馈路径的锁相环PLL。相位检测器驱动锁相环的正向路径中的振荡器。反馈路径包括将振荡器输出连接到相位检测器的分频器。锁相环还包括被配置为控制振荡器的无积分器环路滤波器。无需集成器的环路滤波器可以在PLL用作调制器时降低所需的PLL带宽，而不会降低信号质量。

4. 发明授权

US06993356B2 Frequency generating system for a mobile radio dual-band transceiver 有权
公开(公告)号：US06993356B2
公开(公告)日：2006-01-31
申请号：US09977786
申请日：2001-10-15
申请人： Stefan Herzinger
发明人： Stefan Herzinger
IPC分类号： H04B1/16 , H04B1/38
CPC分类号： H04B1/0053
摘要： In a frequency generating system, a triple/single local-oscillator concept for receiving and transmitting in the lower frequency band, transmitting in the upper frequency band, and receiving in the upper frequency band is used for a dual-band transceiver so that a single band-switched VCO can be used as local oscillator for setting the frequency in all four possible operating cases. The system can be used, for example, in highly integrated dual-band mobile parts for GSM 900/1800 mobile radio.

5. 发明授权

US06658244B2 Method and circuit for compensation control of offset voltages in a radio receiving circuit integrated in a circuit module 失效
公开(公告)号：US06658244B2
公开(公告)日：2003-12-02
申请号：US09922478
申请日：2001-08-03
申请人： Josef Schmal , Timo Gossmann , Georg Lipperer , Stefan Herzinger
发明人： Josef Schmal , Timo Gossmann , Georg Lipperer , Stefan Herzinger
IPC分类号： H04B110
CPC分类号： H04L27/0014 , H03D3/002 , H03F3/45977 , H04L2027/0028 , H04L2027/0057
摘要： Offset voltage compensation in baseband in a radio receiver path is achieved by control and programming signals which are required in any case to set the desired states in the circuit module. For this purpose a sequencer is started which is integrated on the module and provides additional control signals that are defined in time, without any additional computation power being required from a separate baseband processor. The offset voltage compensation can be used in receiver and transceiver chips for portable mobile radios, for example for GSM or PCN/PCS.

6. 发明授权

US06192094B1 Digital phase-frequency detector 有权
标题翻译：数字相位检波器
公开(公告)号：US06192094B1
公开(公告)日：2001-02-20
申请号：US09470622
申请日：1999-12-22
申请人： Helmut Herrmann , Stefan Herzinger
发明人： Helmut Herrmann , Stefan Herzinger
IPC分类号： H03D324
CPC分类号： H03L7/0891 , H03L7/183
摘要： In a digital phase-frequency detector with anti-backlash pulses, which prevent the mapping of very short correction pulses occurring on the basis of small phase differences by use of an AND logic circuit controlling the RESET of two flip flop circuits, a waste time is shortened by reducing a duration of the RESET pulse. The integrable phase-frequency detector according to the invention can be used in fast digital phase-locked control loops, for example for tuners, frequency synthesizers in the field of mobile radio.
摘要翻译：在具有防反向间隙脉冲的数字相位频率检测器中，通过使用控制两个触发器电路的复位的AND逻辑电路来防止基于小的相位差发生的非常短的校正脉冲的映射，浪费时间是通过减少RESET脉冲的持续时间来缩短。根据本发明的可积分相位 - 频率检测器可用于快速数字锁相控制环路，例如用于移动无线电领域的调谐器，频率合成器。

7. 发明授权

US07982547B2 Phase locked loop-based tuning adjustable filter 有权
标题翻译：基于锁相环调谐可调滤波器
公开(公告)号：US07982547B2
公开(公告)日：2011-07-19
申请号：US12414575
申请日：2009-03-30
申请人： Stefan Herzinger
发明人： Stefan Herzinger
IPC分类号： H03L7/24
CPC分类号： H03L7/0812 , H03J3/20 , H03J2200/08
摘要： Phase locked loop based frequency tuning of an adjustable filter is disclosed. A resonant circuit includes the adjustable filter, and an oscillator signal provides an input to the resonant circuit.
摘要翻译：公开了一种可调滤波器的基于锁相环的频率调谐。谐振电路包括可调滤波器，并且振荡器信号为谐振电路提供输入。

8. 发明授权

US07777578B2 Oscillator circuit, in particular for mobile radio 有权
标题翻译：振荡电路，特别适用于移动无线电
公开(公告)号：US07777578B2
公开(公告)日：2010-08-17
申请号：US11394013
申请日：2006-03-30
申请人： Alexander Belitzer , Stefan Herzinger , Giuseppe Li Puma
发明人： Alexander Belitzer , Stefan Herzinger , Giuseppe Li Puma
IPC分类号： H03L7/085
CPC分类号： H03L7/00 , H03B5/1212 , H03B5/1228 , H03B5/124
摘要： An oscillator is disclosed that is tunable to discrete values, and includes a tuning element which can be connected via a switching device. A rectifier circuit is connected to the output of the oscillator and forms a clock signal from the oscillator signal. The oscillator circuit contains a phase delay circuit having a switching input, a clock signal input which is coupled to the output of the rectifier circuit, and a switching output coupled to the switching device. The phase delay circuit has a comparison circuit for comparison of a phase of the clock signal that is applied to the signal input with a reference phase. This phase delay circuit is designed to emit a switching signal after application of an activation signal to the switching input and after the phase of the clock signal which is applied to the signal input matches the reference phase. In consequence, the switching process is delayed until the step-function response of the output signal of the oscillator does not cause a sudden phase change in the clock signal.
摘要翻译：公开了可调谐到离散值的振荡器，并且包括可经由开关装置连接的调谐元件。整流电路连接到振荡器的输出端并形成来自振荡器信号的时钟信号。振荡器电路包括具有开关输入的相位延迟电路，耦合到整流器电路的输出的时钟信号输入和耦合到开关器件的开关输出。相位延迟电路具有用于比较施加到具有参考相位的信号输入的时钟信号的相位的比较电路。该相位延迟电路被设计成在施加到开关输入的激活信号之后并且在施加到信号输入的时钟信号的相位与参考相位匹配之后发出切换信号。因此，切换过程被延迟，直到振荡器的输出信号的阶跃函数响应不会引起时钟信号的突然相位变化。

9. 发明申请

US20070286314A1 DIGITAL RECEIVER SYNCHRONIZATION 有权
标题翻译：数字接收机同步
公开(公告)号：US20070286314A1
公开(公告)日：2007-12-13
申请号：US11753728
申请日：2007-05-25
申请人： Stefan Herzinger , Andreas Menkhoff , Stefan Meier , Norbert Neurohr
发明人： Stefan Herzinger , Andreas Menkhoff , Stefan Meier , Norbert Neurohr
IPC分类号： H04L27/06 , H04L7/00
CPC分类号： H04L7/042
摘要： A method is disclosed, including identifying a preamble in a frame, where the preamble has a preamble length 1. M data items received in succession are stored. The m data items once divided into n portions, where the data items in each portion have respectively been received at successive times and where m and n are natural numbers and the following applies to m and n: m>n, m>1, n>1. The n portions are respectively correlated to the expected values to form component correlation results. Delaying the component correlation results, with at least two component correlation results being delayed by different lengths. The method also includes combining the delayed component correlation results to form a total correlation value. The total correlation value is used to determine whether the m received data items contain the preamble of a frame.
摘要翻译：公开了一种方法，包括识别帧中的前同步码，其中前导码具有前同步码长度1。连续接收的M个数据项被存储。 m个数据项一次划分为n个部分，其中每个部分中的数据项分别在连续的时间被接收，并且其中m和n是自然数，并且以下适用于m和n：m> n，m> 1，n > 1。 n个部分分别与预期值相关以形成分量相关结果。延迟分量相关结果，至少两个分量相关结果被不同长度延迟。该方法还包括组合延迟分量相关结果以形成总相关值。总相关值用于确定m个接收的数据项是否包含帧的前同步码。

10. 发明授权

US09112476B2 Second-order filter with notch for use in receivers to effectively suppress the transmitter blockers 有权
标题翻译：用于接收器的二级滤波器用于有效地抑制发射器阻塞器
公开(公告)号：US09112476B2
公开(公告)日：2015-08-18
申请号：US13405673
申请日：2012-02-27
申请人： Umut Basaran , Josef Schmal , Stefan Herzinger , Herbert Stockinger , Volker Thomas
发明人： Umut Basaran , Josef Schmal , Stefan Herzinger , Herbert Stockinger , Volker Thomas
IPC分类号： H04B1/38 , H03H7/12 , H03H11/12 , H04B1/525 , H03H7/01
CPC分类号： H03H7/0153 , H03H7/06 , H03H7/12 , H03H11/1217 , H03H2007/013 , H04B1/525
摘要： The disclosed invention relates to a transceiver system comprising a notch filter element configured to suppress transmitter blockers (i.e., transmitter interferer signals) within a reception path. In some embodiments, the transceiver front-end comprises a differential reception path, having a first differential branch and a second differential branch, configured to provide an RF differential input signal having a transmitter blocker to a transimpedance amplifier, comprising a first-order active filter and a notch filter element. The notch filter element comprises a stop band corresponding to a frequency of a transmitted signal, such that the notch filter element suppresses the transmitted blocker without degrading the signal quality of the received differential input signal.
摘要翻译：所公开的本发明涉及一种收发器系统，包括陷波滤波器元件，其被配置为抑制接收路径内的发射机阻挡器（即，发射机干扰信号）。在一些实施例中，收发机前端包括具有第一差分支路和第二差分支路的差分接收路径，其被配置为向跨阻抗放大器提供具有发射机阻断器的RF差分输入信号，包括一阶有源滤波器和陷波滤波器元件。陷波滤波器元件包括对应于发送信号的频率的阻带，使得陷波滤波器元件抑制所发送的阻断器而不降低接收的差分输入信号的信号质量。

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