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1. 发明申请

US20090161802A1 RECEIVER WITH ADAPTIVE POWER CONSUMPTION AND A METHOD IMPLEMENTED THEREIN 审中-公开
标题翻译：具有自适应功耗的接收器及其实现的方法
公开(公告)号：US20090161802A1
公开(公告)日：2009-06-25
申请号：US11963482
申请日：2007-12-21
申请人： Pukar Malla , Hasnain Lakdawala , Soumyanath Krishnamurthy
发明人： Pukar Malla , Hasnain Lakdawala , Soumyanath Krishnamurthy
IPC分类号： H04L27/08 , H04B1/10
CPC分类号： H04B1/1036 , H03G3/3068
摘要： A receiver and a method for controlling power consumption therein are disclosed. The receiver comprises at least one front-end module, an amplifier, an Analog to Digital Converter (ADC) module, a spectrum analyzer and a control module. The at least one front-module is configured to receive and process a RF signal to obtain an IF signal. The amplifier is configured to amplify the IF signal received from the at least one front-end module with a variable gain. The ADC module receives the amplified IF signal and converts into a digital signal. Further, the spectrum analyzer estimates a power level of a signal information and a power level of a noise in the digital signal. Thereafter, the control module controls a variable gain of the amplifier and a variable dynamic range of the ADC based on the power level of the signal information and the noise in the digital signal.
摘要翻译：公开了一种用于控制功耗的接收机和方法。接收器包括至少一个前端模块，放大器，模数转换器（ADC）模块，频谱分析器和控制模块。所述至少一个前模块被配置为接收和处理RF信号以获得IF信号。放大器被配置为以可变增益放大从至少一个前端模块接收的IF信号。 ADC模块接收放大的IF信号并转换为数字信号。此外，频谱分析仪估计数字信号中的信号信息的功率电平和噪声的功率电平。此后，控制模块基于信号信息的功率电平和数字信号中的噪声来控制放大器的可变增益和ADC的可变动态范围。

2. 发明申请

US20100052960A1 DUAL DATA WEIGHTED AVERAGE DYNAMIC ELEMENT MATCHING IN ANALOG-TO-DIGITAL 有权
标题翻译：双数据加权平均动态元素匹配模拟数字
公开(公告)号：US20100052960A1
公开(公告)日：2010-03-04
申请号：US12203679
申请日：2008-09-03
申请人： Hasnain Lakdawala , Pukar Malla
发明人： Hasnain Lakdawala , Pukar Malla
IPC分类号： H03M3/00
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464
摘要： Methods and systems to provide dynamic element matching (DEM) in multi-phase sample systems include multiple uncorrelated, dual data weighted averaging, dynamic element matching (DDWA DEM). DDWA DEM may be implemented in a multiple-phase sample system in which sample paths and feedback paths share capacitances. Compensation feedback is apportioned amongst corresponding banks of capacitive sample circuits to utilize the capacitive sample circuits within each bank substantially equally over multiple sample cycles. The apportioning is substantially un-correlated between banks, which may reduce in-band quantization noise folding. DDWA DEM may be implemented within a digital-to-analog converter (DAC), in a delta-sigma modulator.
摘要翻译：在多相样本系统中提供动态元素匹配（DEM）的方法和系统包括多个不相关的双重数据加权平均，动态元素匹配（DDWA DEM）。 DDWA DEM可以在采样路径和反馈路径共享电容的多相采样系统中实现。补偿反馈在相应的电容采样电路组中分配，以在多个采样周期内基本上均等地利用每个存储体中的电容性采样电路。分配在银行之间基本上是不相关的，这可能减少带内量化噪声折叠。 DDWA DEM可以在Δ-Σ调制器中的数模转换器（DAC）内实现。

3. 发明授权

US07760121B2 Dual data weighted average dynamic element matching in analog-to-digital converters 有权
标题翻译：模数转换器中的双数据加权平均动态元件匹配
公开(公告)号：US07760121B2
公开(公告)日：2010-07-20
申请号：US12203679
申请日：2008-09-03
申请人： Hasnain Lakdawala , Pukar Malla
发明人： Hasnain Lakdawala , Pukar Malla
IPC分类号： H03M1/80
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464
摘要： Methods and systems to provide dynamic element matching (DEM) in multi-phase sample systems include multiple uncorrelated, dual data weighted averaging, dynamic element matching (DDWA DEM). DDWA DEM may be implemented in a multiple-phase sample system in which sample paths and feedback paths share capacitances. Compensation feedback is apportioned amongst corresponding banks of capacitive sample circuits to utilize the capacitive sample circuits within each bank substantially equally over multiple sample cycles. The apportioning is substantially un-correlated between banks, which may reduce in-band quantization noise folding. DDWA DEM may be implemented within a digital-to-analog converter (DAC), in a delta-sigma modulator.
摘要翻译：在多相样本系统中提供动态元素匹配（DEM）的方法和系统包括多个不相关的双重数据加权平均，动态元素匹配（DDWA DEM）。 DDWA DEM可以在采样路径和反馈路径共享电容的多相采样系统中实现。补偿反馈在相应的电容采样电路组中分配，以在多个采样周期内基本上均等地利用每个存储体中的电容性采样电路。分配在银行之间基本上是不相关的，这可能减少带内量化噪声折叠。 DDWA DEM可以在Δ-Σ调制器中的数模转换器（DAC）内实现。

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