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1. 发明申请

US20130128662A1 NONVOLATILE MEMORY DEVICE AND METHOD OF READING DATA IN NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和非易失性存储器件中的数据读取方法
公开(公告)号：US20130128662A1
公开(公告)日：2013-05-23
申请号：US13598892
申请日：2012-08-30
申请人： JUNG-HO SONG , JIN-YUB LEE , JAE-WOO IM , SEUNG-JAE LEE , SANG-SO PARK
发明人： JUNG-HO SONG , JIN-YUB LEE , JAE-WOO IM , SEUNG-JAE LEE , SANG-SO PARK
IPC分类号： G11C16/04 , G11C16/26
CPC分类号： G11C11/56 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/3404 , G11C2211/56
摘要： A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.
摘要翻译：提供了一种用于在非易失性存储器件中读取数据的方法。该方法包括对多个多级存储器单元（MLC）执行第一读取操作，对与MLC相对应的至少一个标志单元执行第一感测操作，基于MLC的结果选择性地执行第二读取操作第一感测操作，并且当执行第二读取操作时对所述至少一个标志单元执行第二感测操作。在不执行第二读取操作时，基于第一读取操作和第一感测操作的结果输出读取数据，并且基于第一读取操作，第一感测操作，第二读取操作的结果来输出读取数据以及执行第二读取操作时的第二感测操作。读取数据对应于MLC中的编程数据。

2. 发明申请

US20090059469A1 MULTILAYER CHIP CAPACITOR, CIRCUIT BOARD APPARATUS HAVING THE CAPACITOR, AND CIRCUIT BOARD 有权
标题翻译：多层芯片电容器，具有电容器的电路板装置和电路板
公开(公告)号：US20090059469A1
公开(公告)日：2009-03-05
申请号：US12198342
申请日：2008-08-26
申请人： Byoung Hwa LEE , Sung Kwon WI , Hae Suk CHUNG , Dong Seok PARK , Sang So PARK , Min Cheol PARK
发明人： Byoung Hwa LEE , Sung Kwon WI , Hae Suk CHUNG , Dong Seok PARK , Sang So PARK , Min Cheol PARK
IPC分类号： H01G4/06 , H01G4/228 , H05K7/00
CPC分类号： H01G4/232 , H01G4/012 , H01G4/30 , H01G4/385 , H05K1/0231 , H05K1/113 , H05K2201/09309 , H05K2201/09772 , H05K2201/0979 , H05K2201/10015 , H05K2201/10636 , Y02P70/611
摘要： Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.
摘要翻译：本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极，并且第一至第四内部电极耦合到第一至第四外部电极。第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

3. 发明授权

US6104050A Methods for fabricating integrated circuit devices including etching barrier layers and related structures 失效
标题翻译：集成电路结构，包括蚀刻阻挡层
公开(公告)号：US6104050A
公开(公告)日：2000-08-15
申请号：US2766
申请日：1998-01-05
申请人： Do-hyung Kim , Joo-young Lee , Young-so Park
发明人： Do-hyung Kim , Joo-young Lee , Young-so Park
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/11519 , H01L27/10808 , H01L27/10844 , Y10S257/905 , Y10S438/97
摘要： An integrated circuit device includes a substrate, an insulating layer on the substrate, and a plurality of parallel conductive lines on the insulating layer. An etch barrier is on each of the parallel conductive lines wherein each of the etch barriers comprises a layer of silicon nitride on a respective conductive line and wherein each of the etch barriers further comprises a layer of silicon on the silicon nitride layer. In addition, the device includes a plurality of conductive vias through the insulating layer providing electrical connection to respective surface portions of the substrate, wherein each of the conductive vias is provided in the insulating layer between the etch barriers.
摘要翻译：集成电路器件包括衬底，衬底上的绝缘层和绝缘层上的多个平行导线。每个平行导电线上都有一个蚀刻阻挡层，其中每个蚀刻阻挡层在相应的导电线上包括一层氮化硅，其中每个蚀刻屏障还包括硅氮化物层上的硅层。此外，器件包括通过绝缘层的多个导电通孔，其提供与衬底的相应表面部分的电连接，其中每个导电通孔设置在蚀刻阻挡层之间的绝缘层中。

4. 发明授权

US08760919B2 Nonvolatile memory device and method of reading data in nonvolatile memory device 有权
标题翻译：非易失性存储器件和非易失性存储器件中的数据读取方法
公开(公告)号：US08760919B2
公开(公告)日：2014-06-24
申请号：US13598892
申请日：2012-08-30
申请人： Jung-Ho Song , Jin-Yub Lee , Jae-Woo Im , Seung-Jae Lee , Sang-So Park
发明人： Jung-Ho Song , Jin-Yub Lee , Jae-Woo Im , Seung-Jae Lee , Sang-So Park
IPC分类号： G11C11/56 , G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/3404 , G11C2211/56
摘要： A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.
摘要翻译：提供了一种用于在非易失性存储器件中读取数据的方法。该方法包括：对多个多电平存储器单元（MLC），在对应于MLC中的至少一个标志单元，基于所述结果选择性地执行上的MLC的第二读取操作执行第一读出操作的第一次读操作第一感测操作，并且当执行第二读取操作时对所述至少一个标志单元执行第二感测操作。在不执行第二读取操作时，基于第一读取操作和第一感测操作的结果输出读取数据，并且基于第一读取操作，第一感测操作，第二读取操作的结果来输出读取数据以及执行第二读取操作时的第二感测操作。读取数据对应于MLC中的编程数据。

5. 发明申请

US20060077908A1 Method for generating and authenticating address automatically in IPv6-based internet and data structure thereof 审中-公开
标题翻译：在基于IPv6的互联网及其数据结构中自动生成和认证地址的方法
公开(公告)号：US20060077908A1
公开(公告)日：2006-04-13
申请号：US11081388
申请日：2005-03-15
申请人： So Park , Jae Nah , Kyo Chung
发明人： So Park , Jae Nah , Kyo Chung
IPC分类号： H04L12/28
CPC分类号： H04L29/12216 , H04L29/1232 , H04L61/2007 , H04L61/2092 , H04L63/123 , H04L69/16 , H04L69/161 , H04L69/167
摘要： Provided are a method for automatically generating an address in the IPv6-based Internet when a sender having a pair of a public key and a private key establishes a network connection, and a data format thereof. The method includes generating a CGA address and a CGA option based on the public key and a predetermined parameter, generating a signature option for verifying the CGA option, additionally generating a timestamp option in a case where a unidirectional message is transmitted to the network, and additionally generating a nonce option containing random numbers in a case where a bidirectional message is transmitted to the network, and adding the signature option, the timestamp option and the nonce option to a Neighbor Discovery (ND) option field to form an ND message, and transmitting the ND message to the network. When a host enters the network in a Zero Configuration over the IPv6-based Internet, the host can securely generate its own address without using a manual key. The method can also be applied to general IPv6 packet authentication or position authentication of a mobile node.
摘要翻译：提供了一种当具有一对公钥和私钥的发送方建立网络连接时，在基于IPv6的因特网中自动生成地址的方法及其数据格式。该方法包括基于公共密钥和预定参数生成CGA地址和CGA选项，生成用于验证CGA选项的签名选项，在将单向消息发送到网络的情况下另外生成时间戳选项，以及在将双向消息发送到网络的情况下，另外生成包含随机数的随机数，并将签名选项，时间戳选项和随机数选项添加到邻居发现（ND）选项字段以形成ND消息，以及将ND消息发送到网络。当主机通过基于IPv6的Internet在零配置中进入网络时，主机可以安全地生成自己的地址，而无需使用手动密钥。该方法还可以应用于移动节点的一般IPv6分组认证或位置认证。

6. 发明授权

US5763323A Methods for fabricating integrated circuit devices including etching barrier layers and related structures 失效
标题翻译：用于制造包括蚀刻阻挡层和相关结构的集成电路器件的方法
公开(公告)号：US5763323A
公开(公告)日：1998-06-09
申请号：US687055
申请日：1996-08-07
申请人： Do-hyung Kim , Joo-young Lee , Young-so Park
发明人： Do-hyung Kim , Joo-young Lee , Young-so Park
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/11519 , H01L27/10808 , H01L27/10844 , Y10S257/905 , Y10S438/97
摘要： A method for fabricating an integrated circuit device includes the steps of forming an insulating layer on a substrate and forming a plurality of parallel conductive lines on the insulating layer. An etch barrier is formed on each of the parallel conductive lines, and contact holes are formed between the etch barriers. The contact holes expose portions of the substrate without exposing the plurality of parallel conductive lines. In particular, the contact holes can be formed by forming a patterned mask layer on the insulating layer and etch barriers, and etching exposed portions of the insulating layer. The patterned mask layer selectively exposes a plurality of parallel strips orthogonal to the plurality of parallel conductive lines. Related structures are also discussed.
摘要翻译：一种用于制造集成电路器件的方法包括以下步骤：在衬底上形成绝缘层，并在绝缘层上形成多条平行的导线。在每个平行的导线上形成蚀刻阻挡层，并且在蚀刻阻挡层之间形成接触孔。接触孔露出基板的部分，而不暴露多条平行导线。特别地，可以通过在绝缘层上形成图案化掩模层并蚀刻阻挡层并蚀刻绝缘层的暴露部分来形成接触孔。图案化掩模层选择性地暴露与多个平行导线垂直的多个平行条带。还讨论了相关结构。

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