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1. 发明授权

US09006086B2 Stress regulated semiconductor devices and associated methods 有权
标题翻译：应力调节半导体器件及相关方法
公开(公告)号：US09006086B2
公开(公告)日：2015-04-14
申请号：US13412493
申请日：2012-03-05
申请人： Chien-Min Sung , Ming-Chi Kan , Shao Chung Hu
发明人： Chien-Min Sung , Ming-Chi Kan , Shao Chung Hu
IPC分类号： H01L21/20 , H01L33/64 , H01L23/373 , H01L33/28
CPC分类号： H01L33/641 , H01L23/3732 , H01L23/3733 , H01L33/28 , H01L2924/0002 , H01L2933/0075 , H01L2924/00
摘要： Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.
摘要翻译：提供了受压调节的半导体器件和相关方法。在一个方面，例如，应力调节半导体器件可以包括半导体层，包括形成在半导体层上的碳层的应力调节界面层和耦合到与半导体层相对的碳层的散热器。应力调节界面层是可操作的，以将半导体层和散热器之间的热膨胀系数差减小到或等于约10ppm /℃。

2. 发明授权

US07867892B2 Packaging carrier with high heat dissipation and method for manufacturing the same 有权
标题翻译：具有高散热性的包装载体及其制造方法
公开(公告)号：US07867892B2
公开(公告)日：2011-01-11
申请号：US12071307
申请日：2008-02-20
申请人： Ming-Chi Kan , Shih-Yao Huang , Shao-Chung Hu
发明人： Ming-Chi Kan , Shih-Yao Huang , Shao-Chung Hu
IPC分类号： H01L21/4763
CPC分类号： H01L23/3677 , H01L23/3732 , H01L33/486 , H01L33/641 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates a packaging carrier with high heat dissipation for packaging a chip, comprising: a carrier body, an interfacial metal layer, at least one diamond-like carbon thin film, a plated layer, and an electrode layer. Herein, the packaging carrier further comprises through holes. The present invention further discloses a method for manufacturing the aforementioned packaging carrier, comprising: providing a carrier body; forming an interfacial metal layer on the upper surface of the carrier body; forming a diamond-like carbon thin film on the interfacial metal layer; forming a plated layer on the diamond-like carbon thin film; forming an electrode layer on the lower surface of the carrier body; and forming through holes extending through all or part of the aforementioned elements. The present invention uses a diamond-like carbon thin film and through holes for heat dissipation in three dimensions to improve heat dissipation of an electronic device.
摘要翻译：本发明涉及一种用于包装芯片的具有高散热性的包装载体，包括：载体，界面金属层，至少一个类金刚石碳薄膜，镀层和电极层。这里，包装载体还包括通孔。本发明还公开了一种制造上述包装载体的方法，包括：提供载体; 在载体主体的上表面上形成界面金属层; 在界面金属层上形成类金刚石碳薄膜; 在金刚石状碳薄膜上形成镀层; 在载体主体的下表面上形成电极层; 以及形成贯穿全部或部分上述元件的通孔。本发明使用类金刚石碳薄膜和用于三维散热的通孔来改善电子设备的散热。

3. 发明申请

US20090085180A1 Packaging carrier with high heat dissipation and method for manufacturing the same 有权
标题翻译：具有高散热性的包装载体及其制造方法
公开(公告)号：US20090085180A1
公开(公告)日：2009-04-02
申请号：US12071307
申请日：2008-02-20
申请人： Ming-Chi Kan , Shih-Yao Huang , Shao-Chung Hu
发明人： Ming-Chi Kan , Shih-Yao Huang , Shao-Chung Hu
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/3677 , H01L23/3732 , H01L33/486 , H01L33/641 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates a packaging carrier with high heat dissipation for packaging a chip, comprising: a carrier body, an interfacial metal layer, at least one diamond-like carbon thin film, a plated layer, and an electrode layer. Herein, the packaging carrier further comprises through holes. The present invention further discloses a method for manufacturing the aforementioned packaging carrier, comprising: providing a carrier body; forming an interfacial metal layer on the upper surface of the carrier body; forming a diamond-like carbon thin film on the interfacial metal layer; forming a plated layer on the diamond-like carbon thin film; forming an electrode layer on the lower surface of the carrier body; and forming through holes extending through all or part of the aforementioned elements. The present invention uses a diamond-like carbon thin film and through holes for heat dissipation in three dimensions to improve heat dissipation of an electronic device.
摘要翻译：本发明涉及一种用于包装芯片的具有高散热性的包装载体，包括：载体，界面金属层，至少一个类金刚石碳薄膜，镀层和电极层。这里，包装载体还包括通孔。本发明还公开了一种制造上述包装载体的方法，包括：提供载体; 在载体主体的上表面上形成界面金属层; 在界面金属层上形成类金刚石碳薄膜; 在金刚石状碳薄膜上形成镀层; 在载体主体的下表面上形成电极层; 以及形成贯穿全部或部分上述元件的通孔。本发明使用类金刚石碳薄膜和用于三维散热的通孔来改善电子设备的散热。

4. 发明申请

US20050098892A1 Structure and process of metal interconnects 审中-公开
标题翻译：金属互连的结构和工艺
公开(公告)号：US20050098892A1
公开(公告)日：2005-05-12
申请号：US10718897
申请日：2003-11-20
申请人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
发明人： Shao-Chung Hu , Yu-Ru Yang , Chien-Chung Huang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76886 , H01L21/76805 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867
摘要： A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and the dielectric layer. The film layer is reacted with the metal layer during a thermal process, and a protective layer is formed on the surface of the metal layer. The portion of the film layer not reacted with the metal layer is removed to avoid short between the metal layers. The protective layer can protect the surface of the metal layer from being oxidized and thus the stability and the reliability of the semiconductor device can be effectively promoted.
摘要翻译：提供金属互连的工艺和由其制造的金属互连结构。在电介质层中形成开口。在填充开口的电介质层上形成金属层。在金属层和电介质层上形成膜层。在热处理期间，膜层与金属层反应，在金属层的表面形成保护层。除去与金属层不反应的膜层的部分，以避免金属层之间的短路。保护层可以保护金属层的表面免受氧化，从而可以有效地促进半导体器件的稳定性和可靠性。

5. 发明授权

US06696361B2 Post-CMP removal of surface contaminants from silicon wafer 有权
标题翻译： CMP后移除表面污染物
公开(公告)号：US06696361B2
公开(公告)日：2004-02-24
申请号：US09854006
申请日：2001-05-10
申请人： Shao-Chung Hu , Teng-Chun Tsai , Chia-Lin Hsu , Yung-Tsung Wei
发明人： Shao-Chung Hu , Teng-Chun Tsai , Chia-Lin Hsu , Yung-Tsung Wei
IPC分类号： H01L214763
CPC分类号： H01L21/02074 , H01L21/3212
摘要： A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.
摘要翻译：化学机械抛光（CMP）后从硅晶片去除污染物的方法。在铜化学机械抛光和随后的屏障化学 - 机械抛光操作之后，施加去离子水中的臭氧水溶液以清洁硅晶片，从而去除晶片上的污染物。或者，在铜和阻挡CMP之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。或者，在铜CMP和阻挡CMP两者之后进行臭氧/去离子水缓冲抛光工艺，然后使用化学溶液或去离子水清洁晶片。

6. 发明申请

US20200156946A1 GRAPHENE AND HEXAGONAL BORON NITRIDE PLANES AND ASSOCIATED METHODS 审中-公开
公开(公告)号：US20200156946A1
公开(公告)日：2020-05-21
申请号：US16573804
申请日：2019-09-17
申请人： Chien-Min Sung , Shao Chung Hu , I-Chiao Lin , Chien-Pei Yu
发明人： Chien-Min Sung , Shao Chung Hu , I-Chiao Lin , Chien-Pei Yu
IPC分类号： C01B32/184 , B82Y30/00 , B82Y40/00 , C04B35/583 , C04B35/622 , C04B35/653 , H01L21/02 , C01B32/20 , C23C14/06
摘要： Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate. The graphite film is formed to be substantially free of lattice defects.

7. 发明申请

US20130062627A1 STRESS REGULATED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS 有权
标题翻译：应力调节半导体器件及相关方法
公开(公告)号：US20130062627A1
公开(公告)日：2013-03-14
申请号：US13412493
申请日：2012-03-05
申请人： Chien-Min Sung , Ming-Chi Kan , Shao Chung Hu
发明人： Chien-Min Sung , Ming-Chi Kan , Shao Chung Hu
IPC分类号： H01L33/60 , H01L33/32 , H01L33/34
CPC分类号： H01L33/641 , H01L23/3732 , H01L23/3733 , H01L33/28 , H01L2924/0002 , H01L2933/0075 , H01L2924/00
摘要： Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.
摘要翻译：提供了受压调节的半导体器件和相关方法。在一个方面，例如，应力调节半导体器件可以包括半导体层，包括形成在半导体层上的碳层的应力调节界面层和耦合到与半导体层相对的碳层的散热器。应力调节界面层是可操作的，以将半导体层和散热器之间的热膨胀系数差减小到或等于约10ppm /℃。

8. 发明申请

US20120114932A1 THERMAL CONDUCTION DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：导热装置及其制造方法
公开(公告)号：US20120114932A1
公开(公告)日：2012-05-10
申请号：US13004437
申请日：2011-01-11
申请人： SHAO-CHUNG HU , HSING HUNG , HUNG-CHENG LIN , I-CHIAO LIN , CHIEN-MIN SUNG
发明人： SHAO-CHUNG HU , HSING HUNG , HUNG-CHENG LIN , I-CHIAO LIN , CHIEN-MIN SUNG
IPC分类号： B32B5/16 , B23K31/02
CPC分类号： C09K5/00 , B32B5/16 , B32B15/20 , B32B2264/10 , B32B2307/302 , H01L23/3732 , H01L23/3733 , H01L23/3736 , H01L2924/0002 , Y10T428/25 , H01L2924/00
摘要： A thermal conduction device and a method for fabricating the same are disclosed. Firstly, arrange a plurality of diamond particles on a plane according to a predetermined pattern to form a diamond particle monolayer. Next, apply a forming process on a metal material such that the metal material forms a metal matrix wrapping the diamond particles to form a composite body including the diamond particle monolayer embedded in the metal matrix. Next, stack a plurality of the composite bodies and perform a heating process to join the metal matrixes to each other to form the thermal conduction device. The device is characterized in arranging diamond particles on a plane to form a two-dimensional monolayer structure and manufactured via assembling the two-dimensional monolayer structures to form a three-dimensional multilayer structure. By controlling the arrangement of the diamond particles, the thermal conduction device can have superior thermal conduction performance.
摘要翻译：公开了一种导热装置及其制造方法。首先，根据预定图案在平面上布置多个金刚石颗粒以形成金刚石颗粒单层。接下来，在金属材料上施加成形工艺，使得金属材料形成包裹金刚石颗粒的金属基体，以形成包括嵌入在金属基体中的金刚石颗粒单层的复合体。接下来，堆叠多个复合体并进行加热处理以将金属基体彼此接合以形成导热装置。该装置的特征在于在平面上布置金刚石颗粒以形成二维单层结构，并通过组装二维单层结构制造以形成三维多层结构。通过控制金刚石颗粒的布置，导热装置可以具有优异的导热性能。

9. 发明申请

US20110232950A1 SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：基板及其制造方法
公开(公告)号：US20110232950A1
公开(公告)日：2011-09-29
申请号：US12836393
申请日：2010-07-14
申请人： Shao-Chung HU , Ming-Chi Kan , Chien-Min Sung
发明人： Shao-Chung HU , Ming-Chi Kan , Chien-Min Sung
IPC分类号： H05K1/09 , H05K1/00 , C23F1/02
CPC分类号： H05K1/053 , C23F1/02 , H05K3/06 , H05K2201/0179 , H05K2203/0315 , H05K2203/1147
摘要： The present invention relates to a method for manufacturing a substrate, including: providing a metal base; forming an oxide layer on one surface of the metal base; forming a chemical barrier layer on the oxide layer; forming an intermediate layer on the chemical barrier layer; forming a first metal layer on the intermediate layer; and removing parts of the intermediate layer and the first metal layer by etching to form a first metal wiring layer. Moreover, the present invention may include the following steps alternatively: laminating an insulating adhesive layer and a second metal layer on an exposed area of the chemical barrier layer; forming a second metal wiring layer by etching a part of the second metal layer; forming a surface metal layer; and forming a chip layer on the surface metal layer. The present invention also provides a structure of a substrate obtained according to the aforementioned method.
摘要翻译：本发明涉及一种基板的制造方法，包括：提供金属基体; 在金属基体的一个表面上形成氧化物层; 在氧化物层上形成化学阻挡层; 在化学屏障层上形成中间层; 在所述中间层上形成第一金属层; 以及通过蚀刻去除所述中间层和所述第一金属层的部分以形成第一金属布线层。此外，本发明可以包括以下步骤：在化学阻挡层的暴露区域上层压绝缘粘合剂层和第二金属层; 通过蚀刻所述第二金属层的一部分来形成第二金属布线层; 形成表面金属层; 并在表面金属层上形成芯片层。本发明还提供了根据上述方法获得的基材的结构。

10. 发明申请

US20110127562A1 Electronic Substrate Having Low Current Leakage and High Thermal Conductivity and Associated Methods 审中-公开
标题翻译：具有低电流泄漏和高导热性和相关方法的电子基板
公开(公告)号：US20110127562A1
公开(公告)日：2011-06-02
申请号：US12787074
申请日：2010-05-25
申请人： Chien-Min Sung , Ming Chi Kan , Shao Chung Hu
发明人： Chien-Min Sung , Ming Chi Kan , Shao Chung Hu
IPC分类号： H01L33/00 , H05K1/02 , H05K3/00
CPC分类号： H05K1/053 , H01L23/3735 , H01L2924/0002 , H05K2201/0175 , H05K2201/0179 , H05K2201/0195 , H05K2201/0323 , H05K2203/0315 , Y10T29/49124 , H01L2924/00
摘要： Electrical substrates having low current leakage and high thermal conductivity, including associated methods, are provided. In one aspect for example, a multilayer substrate having improved thermal conductivity and dielectric properties can include a metal layer having a working surface with a local Ra of greater than about 0.1 micron, a dielectric layer coated on the working surface of the metal layer, and a thermally conductive insulating layer disposed on the dielectric layer, wherein the multilayer substrate has a minimum resistivity between the metal layer and the thermally conductive insulating layer across all of the working surface of at least 1×106 ohms.
摘要翻译：提供了具有低电流泄漏和高导热性的电气基板，包括相关方法。在一个方面，例如，具有改善的导热性和介电性能的多层基底可以包括具有局部Ra大于约0.1微米的工作表面的金属层，涂覆在金属层的工作表面上的电介质层，以及布置在所述电介质层上的导热绝缘层，其中所述多层衬底在所述工作表面上的所述金属层和所述导热绝缘层之间具有至少为1×106欧姆的最小电阻率。

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