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    • 3. 发明授权
    • Millimeter-wave switches and attenuators
    • 毫米波开关和衰减器
    • US08279019B2
    • 2012-10-02
    • US12776444
    • 2010-05-10
    • Sean Timothy NicolsonScott Kevin Reynolds
    • Sean Timothy NicolsonScott Kevin Reynolds
    • H01P1/22
    • H03H7/25H01P1/15H04B1/40
    • An input attenuator may include a first input circuit having an RF_IN+ terminal, a first node, a transmission line, a DC blocking capacitor, a second node, a third node, and an output terminal coupled in series, the first node selectively coupled to ground via a serially coupled capacitor and a first silicon germanium heterojunction bipolar transistor, the second node coupled to ground via a capacitor, and the third node selectively coupled to ground via a DC blocking capacitor, a resistor, and a second silicon germanium heterojunction bipolar transistor coupled in series. The input attenuator may also include a second input circuit parallel to the first input circuit and having structure similar to the first input circuit.
    • 输入衰减器可以包括具有RF_IN +端子,第一节点,传输线,隔直流电容器,第二节点,第三节点和串联耦合的输出端的第一输入电路,第一节点选择性地耦合到地 经由串联耦合电容器和第一硅锗异质结双极晶体管,第二节点通过电容器耦合到地,并且第三节点经由隔直流电容器,电阻器和第二硅锗异质结双极晶体管选择性地耦合到地, 系列。 输入衰减器还可以包括与第一输入电路并联并具有与第一输入电路类似的结构的第二输入电路。
    • 5. 发明申请
    • QUADRATURE MODULATION CIRCUITS AND SYSTEMS SUPPORTING MULTIPLE MODULATION MODES AT GIGABIT DATA RATES
    • 支持数字数据速率的多种调制模式的调制电路和系统
    • US20100102895A1
    • 2010-04-29
    • US11486539
    • 2006-07-14
    • Troy James BeukemaAlberto Valdes GarciaScott Kevin Reynolds
    • Troy James BeukemaAlberto Valdes GarciaScott Kevin Reynolds
    • H04L27/20
    • H04L27/0008H04L27/04H04L27/2014H04L27/2057H04L27/206H04L27/362
    • Quadrature modulation systems, circuits and methods are provided to support various modulation modes including ASK (amplitude shift key), FSK (frequency shift key) and PSK (phase shift key) modulation at high data rates (e.g., gigabit data rates). For example, a modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port. The sign modulation control signal can be a digital data signal having binary data encoded into the modulated signal.
    • 提供正交调制系统,电路和方法以支持在高数据速率(例如,千兆比特数据速率)下的ASK(振幅移位键),FSK(频移键)和PSK(相移键)调制的各种调制模式。 例如,调制电路包括具有集成符号调制控制电路和多个混频器端口的混频电路。 混频器端口包括第一输入端口,第二输入端口,输出端口和符号调制控制端口。 调制电路通过使施加到第一输入端口的调制信号与施加到第二输入端口的载波信号相乘的混频器电路的操作产生调制信号,以产生从输出端口输出的混合信号,并且通过集成 符号调制控制电路,响应于输入到符号调制控制端口的符号调制控制信号,控制混频器端口之一处的信号的极性切换。 符号调制控制信号可以是具有被编码为调制信号的二进制数据的数字数据信号。
    • 7. 发明申请
    • Variable-Gain Image-Reject Low-Noise Amplifier
    • 可变增益图像抑制低噪声放大器
    • US20090015335A1
    • 2009-01-15
    • US12127379
    • 2008-05-27
    • Brian Allan FloydScott Kevin Reynolds
    • Brian Allan FloydScott Kevin Reynolds
    • H03G3/00G06F17/50
    • H03F3/16G06F17/5063H03F3/72H03G1/0088
    • A variable-gain amplifier includes an intermediate node operative to receive an electric current from a current source. A common-emitter amplifier has a collector electrically connected to the intermediate node. A first common-base amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to an output node. A base-degenerated amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to the output node. A second common-base amplifier has an emitter electrically connected to the intermediate node and a collector electrically connected to small-signal ground. The intermediate node is operative to direct the electric current to the first common-base amplifier, thereby causing the variable-gain amplifier to operate in a first mode; and the intermediate node is operative to direct the electric current to the base-degenerated amplifier and the second common-base amplifier, thereby causing the variable-gain amplifier to operate in a second mode.
    • 可变增益放大器包括可从电流源接收电流的中间节点。 共发射极放大器具有与中间节点电连接的集电极。 第一公共基极放大器具有电连接到中间节点的发​​射极和电连接到输出节点的集电极。 基极退化放大器具有电连接到中间节点的发​​射极和电连接到输出节点的集电极。 第二公共基极放大器具有电连接到中间节点的发​​射极和电连接到小信号地的集电极。 中间节点可操作地将电流引导到第一共基放大器,从而使可变增益放大器以第一模式工作; 并且中间节点可操作地将电流引导到基极退化的放大器和第二公共基极放大器,从而使可变增益放大器在第二模式下操作。
    • 9. 发明授权
    • Circuits with dynamically biased active loads
    • 具有动态偏置有功负载的电路
    • US5909127A
    • 1999-06-01
    • US601628
    • 1996-02-14
    • Dale Jonathan PearsonScott Kevin Reynolds
    • Dale Jonathan PearsonScott Kevin Reynolds
    • H03K19/013H03K19/017H03K19/086H03K19/094H03K19/173
    • H03K19/01721H03K19/0136H03K19/086H03K19/09432H03K19/1738
    • This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings. The output is sampled and maintained at near ideal bias voltage with a voltage follower type circuit which provides a gain of less than unity and finite delay. Particular circuit implementations using various semiconductor technologies are described and many others are possible. Although the invention may find primary use in VLSI logic circuits, especially those requiring high speed and low power, it is also shown to be useful in analog circuits. Alternate circuit configurations for dynamically biased active load devices are described.
    • 本发明提供一种用动态偏置的有源负载装置代替被动电阻或静态偏置有源负载装置的电路和方法。 这允许负载装置呈现根据电路输出的状态而变化的有效负载。 可以动态优化有效负载和有效负载的时间变化率,以改善电路性能。 根据电路的状态通过使用时间延迟的负反馈来改变有效负载。 负载装置的偏置也能够控制电路的逻辑摆幅。 描述了采用动态偏置的有源负载的偏置发生电路。 这提供了一种用于一系列逻辑电路,特别是CML电路的方法,其以高开关速度在低电压和低功率下工作,具有对称的上升和下降时间以及良好定义的逻辑信号摆幅。 输出采用电压跟随器电路采样并保持在接近理想的偏置电压,该电路提供小于一个和有限延迟的增益。 描述使用各种半导体技术的特定电路实现方式,并且许多其他实施方式是可能的。 尽管本发明可能在VLSI逻辑电路中发现主要用途,特别是那些需要高速度和低功率的逻辑电路,但是它也被证明在模拟电路中是有用的。 描述了用于动态偏置的有源负载装置的备用电路配置。