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    • 2. 发明申请
    • IMAGE ENCODING DEVICE AND IMAGE PROCESSING DEVICE INCLUDING THE SAME
    • 图像编码装置和图像处理装置,包括它们
    • US20130142445A1
    • 2013-06-06
    • US13599089
    • 2012-08-30
    • Deok-Soo PARKHong-Ki KWONByoung-Ju SONGJung-Hyun LIMSang-Hoon HA
    • Deok-Soo PARKHong-Ki KWONByoung-Ju SONGJung-Hyun LIMSang-Hoon HA
    • G06K9/36
    • H04N19/136H04N19/12H04N19/176
    • An image encoding device includes a first compression unit, a second compression unit, a third compression unit and an output unit. The first compression unit generates first compressed data by compressing first data associated with a reference block in an input image. The second compression unit generates second compressed data by compressing second data associated with a current compressing block in the input image when the current compressing block corresponds to a first pattern. The current compressing block is included in the reference block. The third compression unit generates third compressed data by compressing the second data when the current compressing block corresponds to one of a plurality of second patterns. The output unit outputs compressed data based on the first compressed data, the second compressed data and the third compressed data.
    • 图像编码装置包括第一压缩单元,第二压缩单元,第三压缩单元和输出单元。 第一压缩单元通过压缩与输入图像中的参考块相关联的第一数据来生成第一压缩数据。 当当前压缩块对应于第一模式时,第二压缩单元通过压缩与输入图像中的当前压缩块相关联的第二数据来生成第二压缩数据。 当前压缩块包含在参考块中。 当当前压缩块对应于多个第二模式中的一个时,第三压缩单元通过压缩第二数据来生成第三压缩数据。 输出单元基于第一压缩数据,第二压缩数据和第三压缩数据输出压缩数据。
    • 5. 发明申请
    • POWER CONTROL SYSTEM AND POWER AMPLIFICATION SYSTEM USING THE SAME
    • 功率控制系统和功率放大系统
    • US20110193545A1
    • 2011-08-11
    • US12940155
    • 2010-11-05
    • Sang Hoon HAShinichi IIZUKAYoun Suk KIMChul Hwan YOONJun Kyung NA
    • Sang Hoon HAShinichi IIZUKAYoun Suk KIMChul Hwan YOONJun Kyung NA
    • G05F3/16
    • H03F1/0211H03F2200/78
    • There is provided a power control system. A power control system may include: a power regulator having a plurality of power PMOS transistors connected to a power source in parallel with each other; a current sensing unit connected to the power source and sensing currents flowing through a plurality of target PMOS transistors located at predetermined positions; a current mirror unit connected to a first regulated voltage terminal and generating a plurality of currents equal to the currents sensed by the current sensing unit; a comparator unit totaling the plurality of currents generated by the current mirror unit to convert the totaled currents into a voltage, and generating a voltage difference between the voltage and a predetermined reference voltage; and a current bias circuit unit controlling a bias current according to the voltage difference from the comparator unit.There is provided a power amplification system including the power control system.
    • 提供了电源控制系统。 功率控制系统可以包括:功率调节器,具有彼此并联连接到电源的多个功率PMOS晶体管; 连接到电源并感测流过位于预定位置的多个目标PMOS晶体管的电流的电流感测单元; 连接到第一调节电压端子并产生等于由电流感测单元感测的电流的多个电流的电流镜单元; 比较器单元,其将由电流镜单元产生的多个电流合并,以将总电流转换为电压,并产生电压与预定参考电压之间的电压差; 以及电流偏置电路单元,根据与比较器单元的电压差来控制偏置电流。 提供了包括功率控制系统的功率放大系统。
    • 6. 发明申请
    • LOW-DROPOUT REGULATOR
    • 低压差稳压器
    • US20110156677A1
    • 2011-06-30
    • US12859851
    • 2010-08-20
    • Sang Hoon HaSang Hee KimJun Kyung NaShinichi Iizuka
    • Sang Hoon HaSang Hee KimJun Kyung NaShinichi Iizuka
    • G05F1/10
    • G05F1/575
    • There is provided a low-dropout regulator capable of preventing transistors from operating in a triode or deep triode region. A low-dropout regulator according to an aspect of the invention may include: a first operational amplifier having a first input receiving an input voltage; a first P-channel MOSFET having a gate connected to an output of the first operational amplifier, a source connected to a power source terminal, and a drain connected to an output terminal; a feedback circuit providing at least portion of a voltage of the output terminal as a feedback to a second input of the first operational amplifier; and a triode limiter circuit receiving voltages at the source and the gate of the first P-channel MOSFET comparing a voltage difference therebetween with a predetermined reference voltage, and increasing a voltage of the second input of the first operational amplifier when the voltage difference is substantially the same as the reference voltage to thereby prevent the first P-channel MOSFET from entering a triode mode or a deep triode mode.
    • 提供了一种能够防止晶体管在三极管或深三极管区域中工作的低压差稳压器。 根据本发明的一个方面的低压降稳压器可以包括:具有接收输入电压的第一输入的第一运算放大器; 第一P沟道MOSFET,其具有连接到第一运算放大器的输出的栅极,连接到电源端子的源极和连接到输出端子的漏极; 反馈电路,其将所述输出端子的电压的至少一部分提供为所述第一运算放大器的第二输入端的反馈; 以及三极限动器电路,其在所述第一P沟道MOSFET的源极和栅极处接收电压,将其间的电压差与预定参考电压进行比较,并且当所述电压差基本上等于所述第一运算放大器的所述第二输入的电压时, 与参考电压相同,从而防止第一P沟道MOSFET进入三极管模式或深三极管模式。
    • 9. 发明申请
    • Method of compressing a block-based binary image
    • 压缩基于块的​​二进制图像的方法
    • US20090238453A1
    • 2009-09-24
    • US12381553
    • 2009-03-13
    • Sang-hoon HaSang-jo Lee
    • Sang-hoon HaSang-jo Lee
    • G06K9/46G06K9/36
    • G06T9/00G06K9/4642H04N19/103H04N19/136H04N19/176H04N19/182H04N19/186H04N19/593H04N19/94
    • A method of compressing a 2×2 block based binary image is provided. The method includes: determining whether pixels included in a block are included in existing patterns; generating the number N of the pixels included in the existing patterns (N is a natural number); when N is more than a predetermined value, compressing the block with a binary bit stream comprising information about patterns of the pixels included in the existing patterns and color information about the pixels having a new pattern. The method of compressing a 2×2 block based binary image reduces information damage which may occur during compression and restoration of the binary pattern so that the difference in picture quality between an original image and the restored image can be visibly improved.
    • 提供了一种压缩基于2×2块的二值图像的方法。 该方法包括:确定包括在块中的像素是否包括在现有模式中; 生成包括在现有图案中的像素数N(N是自然数); 当N大于预定值时,使用包括关于现有图案中包括的像素的图案的信息的二进制比特流和关于具有新图案的像素的颜色信息来压缩块。 压缩基于2×2块的二进制图像的方法减少了在二进制图案的压缩和恢复期间可能发生的信息损伤,从而可以显着提高原始图像和恢复图像之间的图像质量的差异。
    • 10. 发明授权
    • Voltage level shifter
    • 电压电平转换器
    • US08476957B2
    • 2013-07-02
    • US13309155
    • 2011-12-01
    • Shinichi IizukaJun Kyung NaSang Hoon HaYoun Suk Kim
    • Shinichi IizukaJun Kyung NaSang Hoon HaYoun Suk Kim
    • H03L5/00
    • H03F3/505
    • Provided is a voltage level shifter changing an input voltage level and outputting the input voltage. There is provided the voltage level shifter, including: an operational amplifier having a first input having an applied input voltage thereto; a first MOSFET having a gate connected to an output of the operational amplifier, a source having an applied power thereto, and a drain outputting an output voltage; a voltage dividing resistor unit including a plurality of voltage dividing resistors sequentially connected to the drain of the first MOSFET in series, one connection node between the plurality of voltage dividing resistors being connected to the second input of the operational amplifier; and a second MOSFET having a source and a drain, respectively connected to both ends of at least one of the voltage dividing resistors, and a gate connected to the gate of the first MOSFET.
    • 提供了改变输入电压电平并输出输入电压的电压电平移位器。 提供了电压电平移位器,包括:具有对其施加的输入电压的第一输入的运算放大器; 第一MOSFET,其具有连接到运算放大器的输出的栅极,具有施加功率的源和输出输出电压的漏极; 分压电阻器单元,包括多个分压电阻,其顺序地连接到第一MOSFET的漏极,多个分压电阻器之间的一个连接节点连接到运算放大器的第二输入; 以及分别连接到至少一个分压电阻器的两端的源极和漏极以及连接到第一MOSFET的栅极的栅极的第二MOSFET。