专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090327571A1 COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS 有权
标题翻译：指令处理装置，方法和集成电路装置
公开(公告)号：US20090327571A1
公开(公告)日：2009-12-31
申请号：US12159048
申请日：2006-07-28
申请人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
发明人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
IPC分类号： G06F12/06
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1605 , G06F13/1647 , G06F13/1673 , G09G5/001
摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
摘要翻译：提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。发行单元将选择的命令和读取命令连续地发送到存储装置。

2. 发明申请

US20090100231A1 CACHE MEMORY SYSTEM, AND CONTROL METHOD THEREFOR 有权
标题翻译：缓存记忆系统及其控制方法
公开(公告)号：US20090100231A1
公开(公告)日：2009-04-16
申请号：US11816858
申请日：2006-02-08
申请人： Hazuki Okabayashi , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko
发明人： Hazuki Okabayashi , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko
IPC分类号： G06F12/08
CPC分类号： G06F12/12 , G06F12/0802 , G06F12/0893
摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.
摘要翻译：容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作高速缓存存储器。

3. 发明申请

US20090077318A1 CACHE MEMORY 有权
标题翻译：高速缓存存储器
公开(公告)号：US20090077318A1
公开(公告)日：2009-03-19
申请号：US11910831
申请日：2006-03-17
申请人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0888
摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译：本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中做出了错误的判断。

4. 发明授权

US07454575B2 Cache memory and its controlling method 有权
标题翻译：缓存记忆及其控制方法
公开(公告)号：US07454575B2
公开(公告)日：2008-11-18
申请号：US10583773
申请日：2004-12-21
申请人： Ryuta Nakanishi , Hazuki Okabayashi , Tetsuya Tanaka , Shuji Miyasaka
发明人： Ryuta Nakanishi , Hazuki Okabayashi , Tetsuya Tanaka , Shuji Miyasaka
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0886 , G06F12/127
摘要： The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
摘要翻译：本发明的高速缓冲存储器是具有与保存缓存的数据单位的高速缓存条目相对应的高速缓存条目，表示高速缓存条目是否有效的有效标志，以及指示是否缓存条目已经写入。本发明的高速缓冲存储器包括：改变单元，其基于来自处理器的指令，在高速缓存条目中设置用作标签的地址，并且设置有效标志，而不从存储器加载数据，或者重置在高速缓存条目保存未被写回的重写数据的状态下的脏标志。

5. 发明申请

US20070186048A1 Cache memory and control method thereof 审中-公开
标题翻译：缓存及其控制方法
公开(公告)号：US20070186048A1
公开(公告)日：2007-08-09
申请号：US10599170
申请日：2005-03-16
申请人： Ryuta Nakanishi , Hazuki Okabayashi , Tetsuya Tanaka , Tokuzo Kiyohara
发明人： Ryuta Nakanishi , Hazuki Okabayashi , Tetsuya Tanaka , Tokuzo Kiyohara
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted line data, from the memory to the cache memory; and a touch unit 415 which sets the predicted line address to the cache entry, as a tag, and validates the valid flag, without loading data from the memory into the cache memory
摘要翻译：本发明的高速缓冲存储器包括：预测单元39，其基于从存储器输出的存储器访问的进度，预测下一个预取的行地址。预测单元39包括：预取单元414，其将预测行数据的数据从存储器预取到高速缓冲存储器; 以及触摸单元415，其将预测线路地址设置为高速缓存条目作为标签，并且验证有效标志，而不将数据从存储器加载到高速缓冲存储器

6. 发明授权

US09201819B2 Command processing apparatus, method and integrated circuit apparatus 有权
标题翻译：指令处理装置，方法和集成电路装置
公开(公告)号：US09201819B2
公开(公告)日：2015-12-01
申请号：US12159048
申请日：2006-07-28
申请人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
发明人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
IPC分类号： G06F12/06 , G06F13/16 , G09G5/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1605 , G06F13/1647 , G06F13/1673 , G09G5/001
摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
摘要翻译：提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。发行单元将选择的命令和读取命令连续地发送到存储装置。

7. 发明授权

US07970998B2 Parallel caches operating in exclusive address ranges 有权
标题翻译：在独占地址范围内运行的并行缓存
公开(公告)号：US07970998B2
公开(公告)日：2011-06-28
申请号：US11910831
申请日：2006-03-17
申请人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人： Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0848 , G06F12/0888
摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译：本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中做出了错误的判断。

8. 发明授权

US07904666B2 Access control device, access control integrated circuit, and access control method 有权
标题翻译：访问控制装置，访问控制集成电路和访问控制方法
公开(公告)号：US07904666B2
公开(公告)日：2011-03-08
申请号：US11917574
申请日：2006-07-06
申请人： Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
发明人： Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F9/4887
摘要： In a device, in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. When the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.
摘要翻译：在需要以预定速率访问的主机和需要对访问请求进行响应的处理器访问共享存储器的设备中，提高对处理器的访问请求的响应性，同时主机以预定速率的访问与传统技术相比是有保证的。当主机具有可用于访问共享存储器的资源时，主机以预定速率或更高速度访问共享存储器。当以预定速率或以上执行访问时，处理器通过使用最初分配给主机的资源来访问共享存储器。

9. 发明申请

US20080270658A1 PROCESSOR SYSTEM, BUS CONTROLLING METHOD, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：处理器系统，总线控制方法和半导体器件
公开(公告)号：US20080270658A1
公开(公告)日：2008-10-30
申请号：US12108754
申请日：2008-04-24
申请人： Keisuke KANEKO , Takao YAMAMOTO , Masayuki YAMASAKI , Nobuo HIGAKI , Kazushi KURATA , Ryuta NAKANISHI
发明人： Keisuke KANEKO , Takao YAMAMOTO , Masayuki YAMASAKI , Nobuo HIGAKI , Kazushi KURATA , Ryuta NAKANISHI
IPC分类号： G06F13/372
CPC分类号： G06F13/1663
摘要： Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU0 and PU1 each of which issues an access request for accessing the shared memory, a bus IF unit 4-10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4-10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.
摘要翻译：提供了一种简单结构化的多处理器系统，其在访问共享存储器的多个主单元中均等地分配用于访问共享存储器的访问性能。多处理器系统包括多个主单元PU 0和PU 1，每个主单元PU 0和PU 1发出访问共享存储器的访问请求;总线IF单元4-10，其通过拆分事务方案访问总线，并且单独执行用于接受共享存储器的请求阶段访问请求; 以及用于响应于接受的访问请求执行数据传送的传送阶段。在其中一个主单元连续发出多个接入请求而没有预定时间段的间隔的情况下，总线IF单元4-10将与多个接入请求相对应的连续传输相位执行的数量限制为不大于N 。

10. 发明申请

US20070028055A1 Cache memory and cache memory control method 审中-公开
标题翻译：缓存内存和缓存内存控制方式
公开(公告)号：US20070028055A1
公开(公告)日：2007-02-01
申请号：US10571531
申请日：2004-08-23
申请人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
发明人： Tetsuya Tanaka , Ryuta Nakanishi , Tokuzo Kiyohara , Hiroyuki Morishita , Keishi Chikamura
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/124
摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.
摘要翻译：本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式