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1. 发明授权

US09201819B2 Command processing apparatus, method and integrated circuit apparatus 有权
标题翻译：指令处理装置，方法和集成电路装置
公开(公告)号：US09201819B2
公开(公告)日：2015-12-01
申请号：US12159048
申请日：2006-07-28
申请人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
发明人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
IPC分类号： G06F12/06 , G06F13/16 , G09G5/00
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1605 , G06F13/1647 , G06F13/1673 , G09G5/001
摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
摘要翻译：提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。发行单元将选择的命令和读取命令连续地发送到存储装置。

2. 发明申请

US20070208919A1 BURST MEMORY ACCESS METHOD TO RECTANGULAR AREA 有权
公开(公告)号：US20070208919A1
公开(公告)日：2007-09-06
申请号：US10599832
申请日：2005-03-18
申请人： Takaharu Tanaka , Tetsuji Mochida , Nobuyuki Ichiguchi
发明人： Takaharu Tanaka , Tetsuji Mochida , Nobuyuki Ichiguchi
IPC分类号： G06F12/06
CPC分类号： G06F12/0207 , H04N19/423 , H04N19/43 , H04N19/433
摘要： The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m≦M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n≦N, become successive.
摘要翻译：本发明的信息处理装置包括：存储器1，其是具有突发模式的DRAM，并且在连续的列地址突发传送数据，发出访问请求的主机（13），（14）和（15），以及命令处理单元（11），其转换从每个主机发出的访问请求中包括的访问地址。一个或多个主机访问M×N矩形区域，其中M和N为整数，并且命令处理单元（11）转换访问地址，使得在第（K + m）列处的数据的列地址，其中K和m 是第L行的整数，m <= M，第（L + n）行的第K列的数据的列地址，其中L和n是整数，n <= N成为连续的。

3. 发明授权

US08307190B2 Memory control device, memory device, and memory control method 有权
标题翻译：存储器控制装置，存储器件和存储器控制方法
公开(公告)号：US08307190B2
公开(公告)日：2012-11-06
申请号：US12443598
申请日：2007-12-25
申请人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
发明人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

4. 发明申请

US20090327571A1 COMMAND PROCESSING APPARATUS, METHOD AND INTEGRATED CIRCUIT APPARATUS 有权
标题翻译：指令处理装置，方法和集成电路装置
公开(公告)号：US20090327571A1
公开(公告)日：2009-12-31
申请号：US12159048
申请日：2006-07-28
申请人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
发明人： Nobuyuki Ichiguchi , Tetsuji Mochida , Ryuta Nakanishi , Takaharu Tanaka
IPC分类号： G06F12/06
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/067 , G06F13/1605 , G06F13/1647 , G06F13/1673 , G09G5/001
摘要： A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
摘要翻译：提供了一种命令处理装置和方法，用于最佳地处理从多个主机异步发出的包括多个存储体的存储装置的命令，其中每个主机交替地为存储体0和存储体1发出命令。命令处理装置包括获取从多个主机发出的命令的缓冲器单元，仲裁所获得的命令的仲裁单元和根据仲裁向存储装置发出命令的发布单元。仲裁单元读取在缓冲器单元中获得的多个主器件的命令，并且作为仲裁结果选择一个命令。仲裁单元等待直到与所选择的命令相关的主机的下一个命令变得可读，并读取下一个命令。发行单元将选择的命令和读取命令连续地发送到存储装置。

5. 发明授权

US08738888B2 Memory control device, memory device, and memory control method 有权
标题翻译：存储器控制装置，存储器件和存储器控制方法
公开(公告)号：US08738888B2
公开(公告)日：2014-05-27
申请号：US13615983
申请日：2012-09-14
申请人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
发明人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
IPC分类号： G06F12/12
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

6. 发明授权

US07852343B2 Burst memory access method to rectangular area 有权
标题翻译：突发存储器访问方法到矩形区域
公开(公告)号：US07852343B2
公开(公告)日：2010-12-14
申请号：US10599832
申请日：2005-03-18
申请人： Takaharu Tanaka , Tetsuji Mochida , Nobuyuki Ichiguchi
发明人： Takaharu Tanaka , Tetsuji Mochida , Nobuyuki Ichiguchi
IPC分类号： G09G5/39
CPC分类号： G06F12/0207 , H04N19/423 , H04N19/43 , H04N19/433
摘要： The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m≦M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n≦N, become successive.
摘要翻译：本发明的信息处理装置包括：存储器1，其是具有突发模式的DRAM，并且在连续的列地址突发传送数据，发出访问请求的主机（13），（14）和（15），以及命令处理单元（11），其转换从每个主机发出的访问请求中包括的访问地址。一个或多个主机访问M×N矩形区域，其中M和N是整数，并且命令处理单元（11）转换访问地址，使得在（K + m）列的数据的列地址，其中K m是第L行的m和nlE; M，第（L + n）行的第K列的数据的列地址，其中L和n是整数，并且n＆nlE; N成为连续的。

7. 发明申请

US20100030980A1 MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD 有权
标题翻译：存储器控制装置，存储器装置和存储器控制方法
公开(公告)号：US20100030980A1
公开(公告)日：2010-02-04
申请号：US12443598
申请日：2007-12-25
申请人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
发明人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

8. 发明申请

US20130013879A1 MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD 有权
标题翻译：存储器控制装置，存储器装置和存储器控制方法
公开(公告)号：US20130013879A1
公开(公告)日：2013-01-10
申请号：US13615983
申请日：2012-09-14
申请人： Takashi YAMADA , Daisuke IMOTO , Koji ASAI , Nobuyuki ICHIGUCHI , Tetsuji MOCHIDA
发明人： Takashi YAMADA , Daisuke IMOTO , Koji ASAI , Nobuyuki ICHIGUCHI , Tetsuji MOCHIDA
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

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