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1. 发明授权

US4467518A Process for fabrication of stacked, complementary MOS field effect transistor circuits 失效
标题翻译：堆叠的互补MOS场效应晶体管电路的制造工艺
公开(公告)号：US4467518A
公开(公告)日：1984-08-28
申请号：US464235
申请日：1983-02-07
申请人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
发明人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
IPC分类号： H01L21/268 , H01L21/82 , H01L27/06 , H01L27/092 , H01L29/04 , H01L21/265 , H01L21/225
CPC分类号： H01L21/82 , H01L21/268 , H01L27/0688 , H01L27/0922 , H01L29/04 , Y10S148/164
摘要： A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.
摘要翻译：公开了用于制造以CMOS配置拓扑连接的串联和/或并联的P沟道和N沟道FET器件的方法，其中各个FET器件共享夹在它们之间的公共栅极，形成五个端子器件。还公开了一种新的器件结构和互补MOSFET电路。所公开的方法产生克服现有技术CMOS晶体管的主要缺点的器件和电路，即过度的面积消耗和寄生效应。

2. 发明授权

US3568080A Self-transducing ultrasonic amplifier 失效
标题翻译：自传超声波放大器
公开(公告)号：US3568080A
公开(公告)日：1971-03-02
申请号：US3568080D
申请日：1969-07-23
申请人： RONALD R TROUTMAN
发明人： TROUTMAN RONALD R
IPC分类号： H03F13/00 , H03F3/04
CPC分类号： H03F13/00
摘要： There is disclosed an ultrasonic amplifier for use with microwave signals which does not require transducer elements. A piezoelectric semiconductor element containing current carriers cooperates with a pair of waveguide sections. The microwave signal at the end of one of these sections generates an acoustic signal in the piezoelectric semiconductor element which is amplified by drifting current carriers as it travels down the element. The acoustic signal thereafter excites an electromagnetic signal at the start of the other waveguide section.

3. 发明授权

US4626882A Twin diode overvoltage protection structure 失效
标题翻译：双二极管过压保护结构
公开(公告)号：US4626882A
公开(公告)日：1986-12-02
申请号：US632098
申请日：1984-07-18
申请人： Peter E. Cottrell , William J. Craig , Ronald R. Troutman
发明人： Peter E. Cottrell , William J. Craig , Ronald R. Troutman
IPC分类号： H01L27/08 , H01L21/761 , H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0251 , H01L21/761 , H01L27/0925
摘要： Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD. The doping concentration in the well region is predetermined to have a gradient so that minority carriers injected from one of the diodes in the well region will be repulsed and prevented from moving into the substrate region where they would be majority carriers and they could cause latch-up in the structure or at the very least adversely affect the voltage level of the substrate. Instead the injected carriers recombine in the well region or are collected by the adjacent isolated pocket region.When the second diode is forward biased, the minority carriers are injected into the isolated pocket region and are prevented from reaching the substrate by the underlying well region. This prevents these carriers from affecting the operation of adjacent circuits.
摘要翻译：公开了一种过电压保护结构，当与CMOS电路一起使用时，其保护它们免于过压状况，同时最小化结构中的闩锁状态。它由与衬底相反的导电性的阱区域组成，该阱区限定具有类似于衬底的导电类型的穴区。第一PN结二极管形成在阱区的一部分中，并且第二PN结二极管形成在腔区中。两个二极管具有相反的极性，并且它们都以这样的方式连接到信号线，使得如果信号线上的电压超过电源电压的范围，则两个二极管中的一个将被正向偏置。口袋区域连接到通常接地的VSS端子，并且阱区域连接到电源VDD。阱区中的掺杂浓度被预定为具有梯度，使得从阱区中的二极管中的一个注入的少数载流子将被排斥并被阻止移动到它们将成为多数载流子的衬底区域中，并且它们可能导致闭锁 - 或者至少不利地影响衬底的电压电平。相反，注入的载体在阱区域中重新组合或由相邻的隔离袋区域收集。当第二二极管被正向偏置时，少数载流子被注入到隔离的袋区域中并被下面的阱区域阻止到达衬底。这防止这些载波影响相邻电路的操作。

4. 发明授权

US5546013A Array tester for determining contact quality and line integrity in a TFT/LCD 失效
标题翻译：用于确定TFT / LCD中的接触质量和线路完整性的阵列测试仪
公开(公告)号：US5546013A
公开(公告)日：1996-08-13
申请号：US26897
申请日：1993-03-05
申请人： Yoshikazu Ichioka , Leslie C. Jenkins , Shinichi Kimura , Robert J. Polastre , Ronald R. Troutman , Robert L. Wisnieff
发明人： Yoshikazu Ichioka , Leslie C. Jenkins , Shinichi Kimura , Robert J. Polastre , Ronald R. Troutman , Robert L. Wisnieff
IPC分类号： G01R31/02 , G02F1/13 , G02F1/136 , G02F1/1362 , G02F1/1368 , G09G3/00 , G06F7/02
CPC分类号： G09G3/006 , G02F2001/136254
摘要： An apparatus for testing for and classifying defects in a TFT/LCD array having gate lines and data lines. Devices are provided for activating cells of the array by applying gate pulses to the gate lines and pulses to the data lines. Devices are also provided for acquiring waveforms from data lines of the array. Additional devices sample the waveforms at selected points in time. A computer may be used to classify the waveforms to indicate whether defects are present and if present, the nature of the defects by comparing voltages of the waveform at the selected points in time.
摘要翻译：一种用于测试和分类具有栅极线和数据线的TFT / LCD阵列中的缺陷的装置。提供了用于通过向栅极线施加栅极脉冲并将脉冲施加到数据线来激活阵列的单元的装置。还提供了用于从阵列的数据线获取波形的装置。附加设备在选定的时间点对波形进行采样。可以使用计算机对波形进行分类，以指示是否存在缺陷，如果存在缺陷，则通过比较所选择的时间点上的波形的电压来确定缺陷的性质。

5. 发明授权

US4462151A Method of making high density complementary transistors 失效
标题翻译：制造高密度互补晶体管的方法
公开(公告)号：US4462151A
公开(公告)日：1984-07-31
申请号：US446793
申请日：1982-12-03
申请人： Henry J. Geipel, Jr. , Ronald R. Troutman , John M. Wursthorn
发明人： Henry J. Geipel, Jr. , Ronald R. Troutman , John M. Wursthorn
IPC分类号： H01L27/08 , H01L21/8238 , H01L29/06 , H01L29/49 , H01L29/78 , H01L21/22 , H01L11/14
CPC分类号： H01L29/495 , H01L21/823814 , H01L21/823828 , H01L29/0638 , H01L29/4975
摘要： A simple process is provided which forms a bulk CMOS structure by depositing a layer of material which resists oxidation, e.g., a barrier layer of silicon nitride on an N- semiconductor substrate, forming a P well in the substrate through a given segment of the barrier layer, removing a first segment of the barrier layer to form N+ regions for N channel source and drain and N- substrate contact, removing a second segment of the barrier layer to form a P+ field region, removing a third segment of the barrier layer to form P+ regions for source and drain of a P channel device, forming a first control electrode having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode between the N channel source and drain regions having a work function different from that of the first control electrode.
摘要翻译：提供了一种简单的方法，其通过沉积抗氧化的材料层（例如，在N-半导体衬底上的氮化硅阻挡层）形成体CMOS结构，通过势垒的给定段在衬底中形成P阱去除阻挡层的第一段以形成用于N沟道源极和漏极和N-衬底接触的N +区域，去除阻挡层的第二部分以形成P +场区域，去除阻挡层的第三部分到形成用于P沟道器件的源极和漏极的P +区域，形成具有作为离子屏障的P沟道器件的给定功函数的第一控制电极，然后在具有N沟道源极和漏极区域的N沟道源极和漏极区域之间形成第二控制电极，与第一控制电极不同的功函数。

6. 发明授权

US5739545A Organic light emitting diodes having transparent cathode structures 失效
标题翻译：具有透明阴极结构的有机发光二极管
公开(公告)号：US5739545A
公开(公告)日：1998-04-14
申请号：US794072
申请日：1997-02-04
申请人： Supratik Guha , Richard Alan Haight , Joseph M. Karasinski , Ronald R. Troutman
发明人： Supratik Guha , Richard Alan Haight , Joseph M. Karasinski , Ronald R. Troutman
IPC分类号： H01L51/50 , H01L51/52 , H05B33/12 , H05B33/14 , H05B33/22 , H05B33/26 , H01L35/24 , H01L51/00
CPC分类号： H01L51/5234 , H01L2251/5323
摘要： Organic light emitting diodes having a transparent cathode structure is disclosed. The structure consists of a low work function metal in direct contact with the electron transport layer of the OLED covered by a layer of a wide bandgap semiconductor. Calcium is the preferred metal because of its relatively high optical transmissivity for a metal and because of its proven ability to form a good electron injecting contact to organic materials. ZnSe, ZnS or an alloy of these materials are the preferred semiconductors because of their good conductivity parallel to the direction of light emission, their ability to protect the underlying low work function metal and organic films and their transparency to the emitted light. Arrays of these diodes, appropriately wired, can be used to make a self-emissive display. When fabricated on a transparent substrate, such a display is at least partially transparent making it useful for heads-up display applications in airplanes and automobiles. Such a display can also be fabricated on an opaque substrate, such as silicon, in which previously fabricated devices and circuits can be used to drive the display.
摘要翻译：公开了具有透明阴极结构的有机发光二极管。该结构由与宽带隙半导体层覆盖的OLED的电子传输层直接接触的低功函数金属组成。由于金属具有相对较高的透光率，因此，由于已证明能够与有机材料形成良好的电子注入接触，钙是优选的金属。 ZnSe，ZnS或这些材料的合金是优选的半导体，因为它们具有与光发射方向平行的良好导电性，它们保护下层低功函数金属和有机膜的能力及其对发射光的透明度。这些二极管的数组，适当连接，可用于进行自发光显示。当在透明基板上制造时，这种显示器至少部分透明，使其对于在飞机和汽车中的单机显示应用是有用的。这种显示器也可以在诸如硅的不透明衬底上制造，其中可以使用先前制造的器件和电路来驱动显示器。

7. 发明授权

US4382229A Channel hot electron monitor 失效
标题翻译：通道热电子监视器
公开(公告)号：US4382229A
公开(公告)日：1983-05-03
申请号：US210937
申请日：1980-11-28
申请人： Peter E. Cottrell , Ronald R. Troutman
发明人： Peter E. Cottrell , Ronald R. Troutman
IPC分类号： G01R31/26 , G01R31/22
CPC分类号： G01R31/2621
摘要： This teaches that by measuring the rate of change in gate current of an insulating gate field effect transistor, under normal operating conditions, the time required to achieve a predetermined change in source-to-drain current in the transistor can be found. Because changes in gate current depends more on sensitivity on charge trapping in the oxide than do changes in channel current, and since the gate current occurs only in the small region of electron emission, the effects on gate current are more quickly developed than the secondary effect of reduced channel current due to the charge in gate oxide caused by the presence of trapped electrons.
摘要翻译：这表明，通过测量绝缘栅场效应晶体管的栅极电流的变化率，在正常工作条件下，可以找到实现晶体管中源极 - 漏极电流的预定变化所需的时间。因为栅极电流的变化更多地取决于在沟道电流中改变氧化物中的电荷捕获的灵敏度，并且由于栅极电流仅发生在电子发射的小区域中，所以对栅极电流的影响比次级效应更快地发展由于俘获电子的存在引起的栅极氧化物中的电荷引起的沟道电流减小。

8. 发明授权

US4670669A Charge pumping structure for a substrate bias generator 失效
标题翻译：用于衬底偏置发生器的电荷泵浦结构
公开(公告)号：US4670669A
公开(公告)日：1987-06-02
申请号：US640421
申请日：1984-08-13
申请人： Peter E. Cottrell , William J. Craig , Ronald R. Troutman
发明人： Peter E. Cottrell , William J. Craig , Ronald R. Troutman
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H03K3/354
CPC分类号： H01L27/0222
摘要： A charge pumping structure is disclosed for use in a substrate bias voltage generator. It includes a capacitor on a substrate region for coupling to a first node periodic voltage signals received at a second node. A first diode structure provides a current path from the first node to the substrate and a second diode structure provides a current path between the first node and a reference potential, which is typically the ground. The first diode structure includes a PN junction diode, an isolation ring for collecting minority charge carriers injected into the substrate and is constructed on a portion of the substrate that has a lower doping concentration than the underlying substrate portion establishing a built-in electric field which inhibits the flow of minority carriers from the first diode to the underlying substrate. The second diode structure may include a pocket type PN junction diode constructed so that majority carriers are prevented from moving back into the substrate from which the substrate bias voltage generator will have to remove them.
摘要翻译：公开了用于衬底偏置电压发生器的电荷泵送结构。它包括在衬底区域上的电容器，用于耦合到第一节点在第二节点处接收的周期性电压信号。第一二极管结构提供从第一节点到衬底的电流路径，并且第二二极管结构提供第一节点和通常为地的参考电位之间的电流路径。第一二极管结构包括PN结二极管，用于收集注入到衬底中的少数电荷载流子的隔离环，并且构建在衬底的一部分上，该衬底具有比下面的衬底部分更低的掺杂浓度，建立内置的电场，抑制少数载流子从第一二极管流到下面的衬底。第二二极管结构可以包括袖珍型PN结二极管，其被构造成使得多数载流子被阻止移回到衬底中，衬底偏置电压发生器将从该衬底移除它们。

9. 发明授权

US4558508A Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step 失效
标题翻译：使用单个掩蔽步骤制造具有对准场掺杂的双阱CMOS半导体结构的工艺
公开(公告)号：US4558508A
公开(公告)日：1985-12-17
申请号：US660673
申请日：1984-10-15
申请人： Wayne I. Kinney , Charles W. Koburger, III , Jerome B. Lasky , Larry A. Nesbit , Ronald R. Troutman , Francis R. White
发明人： Wayne I. Kinney , Charles W. Koburger, III , Jerome B. Lasky , Larry A. Nesbit , Ronald R. Troutman , Francis R. White
IPC分类号： H01L27/08 , H01L21/033 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L21/22 , H01L21/265 , H01L29/78
CPC分类号： H01L21/76218 , H01L21/033 , H01L21/823892 , H01L29/0638 , H01L27/0928 , Y10S148/043 , Y10S148/053 , Y10S148/10 , Y10S148/157
摘要： A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.
摘要翻译：制造具有场隔离掺杂的CMOS双阱半导体结构的方法，其中仅需要单个光刻掩模步骤，以提供阱彼此之间的自对准以及对阱的场隔离掺杂区域的自对准。光刻掩模步骤形成了良好的掩模，并且限定了一种氧化屏障，其作用为在一种类型的场掺杂剂的离子注入期间的注入掩模（吸收体）在相对孔的氧化期间在一个阱上形成氧化屏障，以在一个阱上形成牺牲氧化物层，其形成用于随后形成场掺杂区域的对准标记; 以及在由牺牲氧化物同时吸收的相反型场掺杂剂的离子注入期间的掺杂剂发射器。结果，形成了与阱自对准的场掺杂氧化物层，使得通过随后的掩模步骤，在掺杂的氧化物层上限定氧化物场隔离。然后使用热循环将场掺杂剂驱动到相应的场掺杂区域中。

10. 发明授权

US4555721A Structure of stacked, complementary MOS field effect transistor circuits 失效
标题翻译：堆叠的互补MOS场效应晶体管电路的结构
公开(公告)号：US4555721A
公开(公告)日：1985-11-26
申请号：US548733
申请日：1983-11-04
申请人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
发明人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
IPC分类号： H01L21/268 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/04 , H01L27/02
CPC分类号： H01L21/268 , H01L21/8238 , H01L27/0688 , H01L27/0922 , H01L29/04
摘要： A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.
摘要翻译：公开了用于制造以CMOS配置拓扑连接的串联和/或并联的P沟道和N沟道FET器件的方法，其中各个FET器件共享夹在它们之间的公共栅极，形成五个端子器件。还公开了一种新的器件结构和互补MOSFET电路。所公开的方法产生克服现有技术CMOS晶体管的主要缺点的器件和电路，即过度的面积消耗和寄生效应。

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