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1. 发明授权

US4467518A Process for fabrication of stacked, complementary MOS field effect transistor circuits 失效
标题翻译：堆叠的互补MOS场效应晶体管电路的制造工艺
公开(公告)号：US4467518A
公开(公告)日：1984-08-28
申请号：US464235
申请日：1983-02-07
申请人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
发明人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
IPC分类号： H01L21/268 , H01L21/82 , H01L27/06 , H01L27/092 , H01L29/04 , H01L21/265 , H01L21/225
CPC分类号： H01L21/82 , H01L21/268 , H01L27/0688 , H01L27/0922 , H01L29/04 , Y10S148/164
摘要： A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.
摘要翻译：公开了用于制造以CMOS配置拓扑连接的串联和/或并联的P沟道和N沟道FET器件的方法，其中各个FET器件共享夹在它们之间的公共栅极，形成五个端子器件。还公开了一种新的器件结构和互补MOSFET电路。所公开的方法产生克服现有技术CMOS晶体管的主要缺点的器件和电路，即过度的面积消耗和寄生效应。

2. 发明授权

US4555721A Structure of stacked, complementary MOS field effect transistor circuits 失效
标题翻译：堆叠的互补MOS场效应晶体管电路的结构
公开(公告)号：US4555721A
公开(公告)日：1985-11-26
申请号：US548733
申请日：1983-11-04
申请人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
发明人： Jai P. Bansal , Claude L. Bertin , Ronald R. Troutman
IPC分类号： H01L21/268 , H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/04 , H01L27/02
CPC分类号： H01L21/268 , H01L21/8238 , H01L27/0688 , H01L27/0922 , H01L29/04
摘要： A method is disclosed for fabricating series and/or parallel connected P channel and N channel FET device topologically connected in a CMOS configuration, where the individual FET devices share a common gate sandwiched between them, forming a five terminal device. A new device structure and complementary MOSFET circuitry is also disclosed. The disclosed process produces devices and circuits which overcome the main disadvantage of prior art CMOS transistors, namely excessive area consumption and parasitic effects.
摘要翻译：公开了用于制造以CMOS配置拓扑连接的串联和/或并联的P沟道和N沟道FET器件的方法，其中各个FET器件共享夹在它们之间的公共栅极，形成五个端子器件。还公开了一种新的器件结构和互补MOSFET电路。所公开的方法产生克服现有技术CMOS晶体管的主要缺点的器件和电路，即过度的面积消耗和寄生效应。

3. 发明授权

US07895559B2 Method for designing structured ASICs in silicon processes with three unique masking steps 有权
标题翻译：在硅工艺中设计具有三个独特掩蔽步骤的结构化ASIC的方法
公开(公告)号：US07895559B2
公开(公告)日：2011-02-22
申请号：US12218672
申请日：2008-07-17
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
摘要翻译：多功能核心基站包括一组功能微电路。这些微电路用于设计逻辑函数库。由一个或多个微电路组成的功能宏具有类似于常规标准单元库宏集的固定和完整的物理布局。除了核心功能宏集之外，库中还定义了主输入/输出缓冲区和常用的单端口和双端口存储器块。该库包括所有的ASIC综合，仿真和物理设计规则。

4. 发明授权

US07239177B2 High voltage tolerant off chip driver circuit 有权
标题翻译：高耐压片外驱动电路
公开(公告)号：US07239177B2
公开(公告)日：2007-07-03
申请号：US11107607
申请日：2005-04-15
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： H03K19/0175
CPC分类号： H03K19/00315
摘要： An off chip driver circuit includes a pre-driver circuit and a driver circuit. Driver data and enable inputs are decoded in the pre-driver circuit to provide independent inputs to pull up and pull down transistors in the driver circuit. The enable input keeps the driver circuit in the active or high impedance modes. A feedback signal generated by the driver output and the driver enable signals controls an inverter circuit within the driver circuit to provide proper biasing conditions at the gate of the pull up transistor. This feed back provides fast switching times for the driver circuit and prevents gate oxide of all the transistors from being overstressed by the external high voltage signal.
摘要翻译：片外驱动电路包括预驱动电路和驱动电路。驱动器数据和使能输入在预驱动器电路中被解码，以提供独立的输入以在驱动器电路中上拉和下拉晶体管。使能输入保持驱动电路处于有效或高阻抗模式。由驱动器输出和驱动器使能信号产生的反馈信号控制驱动器电路内的反相器电路，以在上拉晶体管的栅极处提供适当的偏置条件。该反馈提供了驱动电路的快速切换时间，并且防止所有晶体管的栅极氧化物被外部高电压信号过载。

5. 发明授权

US4418401A Latent image ram cell 失效
标题翻译：潜图图像柱塞细胞
公开(公告)号：US4418401A
公开(公告)日：1983-11-29
申请号：US454314
申请日：1982-12-29
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： G11C11/411 , G11C7/20 , G11C11/41 , G11C17/00 , G11C11/40
CPC分类号： G11C7/20
摘要： An asymmetric RAM cell is disclosed which will have a predictable initial storage state when pulsed drain voltage is turned on and yet after the initial turn-on interval, will operate in a symmetric fashion storing either binary ones or zeros. Thus, an initial prestored set of information can be permanently provided in a memory array made up of such cells, by orienting each individual cell at the time of manufacture so as to selectively represent either a binary one or zero. This is illustrated in the FIGURE where the upper cell has a first state by virtue of its orientation and the lower cell has a second, opposite state by virtue of its relative opposite orientation. When the array is turned on, the upper cell will have the opposite binary state from the lower cell. Thereafter, each cell can be respectively switched for storing ones and zeros in a normal RAM operating mode.
摘要翻译：公开了一种非对称RAM单元，当脉冲漏极电压接通并且在初始接通间隔之后将具有可预测的初始存储状态，将以存储二进制或零的对称方式操作。因此，通过在制造时定向每个单独的单元以便选择性地表示二进制1或零，可以将初始预存储的信息集永久地提供在由这样的单元组成的存储器阵列中。这在图中示出，其中上部单元凭借其取向具有第一状态，并且下部单元由于其相对相对的取向具有第二相反的状态。当阵列打开时，上部单元格将具有与下部单元格相反的二进制状态。此后，可以分别切换每个单元以在正常RAM操作模式下存储零和零。

6. 发明授权

US08975920B2 Programmable transceiver circuit 有权
标题翻译：可编程收发电路
公开(公告)号：US08975920B2
公开(公告)日：2015-03-10
申请号：US13584375
申请日：2012-08-13
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： H03K19/094 , H03K3/011 , H03K19/0185
CPC分类号： H03K3/011 , H03K19/018585
摘要： A multi-function programmable transceiver is described. The transceiver includes a driver circuit and a receiver circuit, which allows an Application Specific Integrated Circuit (ASIC) device to drive and receive data from other ASIC devices. Both the driver and receiver circuits share a common input/output (I/O) pin. The driver circuit can be programmed to provide one of the several driver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS. Other functional features of the transceiver that can be programmed are driving strengths or output impedance, output power supply voltage, single ended or differential mode of HSTL/SSTL transceivers, and class 1 or class 2 operations for SSTL/HSTL transceivers. The receiver circuit can also be programmed to provide one of the several receiver functions, such as CMOS, TTL, PCI, HSTL, SSTL and LVDS.
摘要翻译：描述了多功能可编程收发器。收发器包括驱动器电路和接收器电路，其允许专用集成电路（ASIC）装置来驱动和接收来自其它ASIC装置的数据。驱动器和接收器电路都共享一个公共输入/输出（I / O）引脚。可以将驱动电路编程为提供CMOS，TTL，PCI，HSTL，SSTL和LVDS等多种驱动功能之一。可编程的收发器的其他功能特性是驱动强度或输出阻抗，输出电源电压，HSTL / SSTL收发器的单端或差分模式，以及SSTL / HSTL收发器的1类或2类操作。接收机电路也可以编程为提供几种接收机功能之一，如CMOS，TTL，PCI，HSTL，SSTL和LVDS。

7. 发明授权

US06765245B2 Gate array core cell for VLSI ASIC devices 有权
标题翻译：用于VLSI ASIC器件的门阵列核心单元
公开(公告)号：US06765245B2
公开(公告)日：2004-07-20
申请号：US10325030
申请日：2002-12-19
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： H01L2710
CPC分类号： H01L27/11807 , Y10S257/909
摘要： A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly. This core cell design reduces the overall wiring lengths, parasitic capacitance, which in turn reduce delays, power dissipation and increase ASIC performance and circuit density. Gate array ASIC components designed using this core cell provide circuit density, performance and power dissipation characteristics comparable to the Standard Cell ASICs but with the advantage of reducing the mask cost and processing time by about 50 percent.
摘要翻译：一种非常有效的栅极阵列核心单元，其中基极单元由一组6个PMOS晶体管和一组6个NMOS晶体管组成。它还包括6个PMOS晶体管中的2个预布线，6个NMOS晶体管中的2个处于多晶硅级或局部互连级，同时留下剩余的PMOS和NMOS晶体管作为在功能ASIC金属化工艺期间互连的独立晶体管。核心单元还具有嵌入其中的2个多晶硅或局部互连线，可用于互连晶体管用于逻辑功能实现。在本发明中定义的核心单元是高度灵活的，并且已被分析以互连ASIC设计所需的所有类型的逻辑和存储器功能。晶体管的布局，多晶硅级别或局部互连级别的策略晶体管的预接线以及嵌入式多晶硅或局部互连电线显着降低了核心单元尺寸。这种核心单元设计减少了总体布线长度，寄生电容，从而降低延迟，功耗，提高ASIC性能和电路密度。使用该核心单元设计的门阵列ASIC组件提供与标准单元ASIC相当的电路密度，性能和功耗特性，但具有将掩模成本和处理时间降低约50％的优势。

8. 发明申请

US20080282216A1 Method for designing structured ASICs in silicon processes with three unique masking steps 有权
标题翻译：在硅工艺中设计具有三个独特掩蔽步骤的结构化ASIC的方法
公开(公告)号：US20080282216A1
公开(公告)日：2008-11-13
申请号：US12218672
申请日：2008-07-17
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
摘要翻译：多功能核心基站包括一组功能微电路。这些微电路用于设计逻辑函数库。由一个或多个微电路组成的功能宏具有类似于常规标准单元库宏集的固定和完整的物理布局。除了核心功能宏集之外，库中还定义了主输入/输出缓冲区和常用的单端口和双端口存储器块。该库包括所有的ASIC综合，仿真和物理设计规则。

9. 发明授权

US5858817A Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step 失效
标题翻译：个性化主切片晶片的过程，并用单一掩蔽步骤制造高密度VLSI部件
公开(公告)号：US5858817A
公开(公告)日：1999-01-12
申请号：US728880
申请日：1996-10-10
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： H01L27/118 , H01L21/70
CPC分类号： H01L27/118
摘要： A method of making gate array ASIC components from a master slice wafer having a first conducting layer containing logic elements, a second conducting layer containing first electrically conducting elements extending in a first direction, and a third conducting layer comprises interconnecting at least some of the logic elements to one another with a single masking process step by defining, on the third conducting layer, second conducting elements connected to the first electrically conducting elements to define connections between the logic elements.
摘要翻译：一种从具有包含逻辑元件的第一导电层的母片晶片制作栅极阵列ASIC元件的方法，包含沿第一方向延伸的第一导电元件的第二导电层和第三导电层，包括互连至少一些逻辑元件通过在第三导电层上限定连接到第一导电元件的第二导电元件以限定逻辑元件之间的连接，通过单个掩模处理步骤将元件彼此分开。

10. 发明授权

US07418692B2 Method for designing structured ASICS in silicon processes with three unique masking steps 有权
标题翻译：在具有三个独特掩蔽步骤的硅工艺中设计结构化ASICS的方法
公开(公告)号：US07418692B2
公开(公告)日：2008-08-26
申请号：US11147024
申请日：2005-06-07
申请人： Jai P. Bansal
发明人： Jai P. Bansal
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.
摘要翻译：多功能核心基站包括一组功能微电路。这些微电路用于设计逻辑函数库。由一个或多个微电路组成的功能宏具有类似于常规标准单元库宏集的固定和完整的物理布局。除了核心功能宏集之外，库中还定义了主输入/输出缓冲区和常用的单端口和双端口存储器块。该库包括所有的ASIC综合，仿真和物理设计规则。

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