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1. 发明授权

US08560899B2 Safe memory storage by internal operation verification 有权
标题翻译：通过内部操作验证安全内存存储
公开(公告)号：US08560899B2
公开(公告)日：2013-10-15
申请号：US12847450
申请日：2010-07-30
申请人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder , Glenn Ashley Farrall
发明人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder , Glenn Ashley Farrall
IPC分类号： G06F11/00
CPC分类号： G11C29/44 , G11C29/024 , G11C29/025 , G11C2029/0411
摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
摘要翻译：所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。再生地址签名可以与请求的存储器地址位置进行比较。如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发，字线和/或位线是连续的。

2. 发明授权

US08112683B1 System and application debugging 有权
标题翻译：系统和应用程序调试
公开(公告)号：US08112683B1
公开(公告)日：2012-02-07
申请号：US12025600
申请日：2008-02-04
申请人： Robert Wiesner , Guido Kehrle
发明人： Robert Wiesner , Guido Kehrle
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R31/318569 , G06F11/267
摘要： Systems, apparatuses, and methods for system and application debugging are described herein. A tested platform may include a debug event monitor in a boundary scan interface that detects a debug event in a process and determines a characteristic associated with the debug event. The debug event monitor may trigger an application debug event or a boundary scan debug event based at least in part on the determined characteristic. Other embodiments may be described and claimed.
摘要翻译：本文描述了用于系统和应用调试的系统，装置和方法。经测试的平台可以包括在边界扫描接口中的调试事件监视器，其检测进程中的调试事件并确定与调试事件相关联的特性。调试事件监视器可以至少部分地基于所确定的特性来触发应用调试事件或边界扫描调试事件。可以描述和要求保护其他实施例。

3. 发明申请

US20090059678A1 Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device 有权
标题翻译：存储单元布置，用于控制存储单元，存储器阵列和电子设备的方法
公开(公告)号：US20090059678A1
公开(公告)日：2009-03-05
申请号：US12049132
申请日：2008-03-14
申请人： Robert Strenz , Wolfram Langheinrich , Mayk Roehrich , Robert Wiesner
发明人： Robert Strenz , Wolfram Langheinrich , Mayk Roehrich , Robert Wiesner
IPC分类号： G11C16/02 , G11C11/40
CPC分类号： G11C16/0425 , G11C16/10 , H01L29/66825 , H01L29/7881
摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.
摘要翻译：在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除。

4. 发明授权

US07060558B2 Method for fabricating a field-effect transistor having a floating gate 失效
公开(公告)号：US07060558B2
公开(公告)日：2006-06-13
申请号：US10320950
申请日：2002-12-16
申请人： Franz Hofmann , Georg Tempel , Robert Strenz , Robert Wiesner
发明人： Franz Hofmann , Georg Tempel , Robert Strenz , Robert Wiesner
IPC分类号： H01L21/336 , H01L21/425 , H01L21/3205 , H01L21/44 , H01L21/469
CPC分类号： H01L21/28273 , H01L29/42384
摘要： In the course of a method for fabricating a field-effect transistor having a floating gate, a structure is formed which has uncovered sidewalls of a layer made of the material for forming the floating gate and which is exposed to an oxidizing atmosphere in order to coat the sidewalls. At the same time, other regions of the structure have an insulating oxide layer. At a point in time prior to the action of an oxidizing atmosphere, nitrogen is implanted into the material of the floating gate in a quantity that appreciably reduces the oxidation at the sidewalls thereof.

5. 发明申请

US20140075093A1 METHOD AND SYSTEM FOR IMPLICIT OR EXPLICIT ONLINE REPAIR OF MEMORY 审中-公开
标题翻译：隐含或明示在线修复记忆的方法和系统
公开(公告)号：US20140075093A1
公开(公告)日：2014-03-13
申请号：US13612097
申请日：2012-09-12
申请人： Robert Wiesner , Rudolf Ullmann , Walter Mischo , Jens Rosenbusch
发明人： Robert Wiesner , Rudolf Ullmann , Walter Mischo , Jens Rosenbusch
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F12/0246 , G06F2212/7202 , G11C11/41 , G11C29/4401 , G11C29/76 , G11C29/82 , G11C2029/0409
摘要： Systems and methods related to a memory device are provided. The systems and methods include using at least one driver with predetermined reduced driving capability to drive at least one of the memory elements of the memory device in a reliable detection algorithm. The at least one driver has reduced driving capability compared to a driver used for standard read access. The reliable detection algorithm can include detecting failing memory elements on a respective reading current diverging from an expected or expectable reading current.
摘要翻译：提供了与存储器件相关的系统和方法。该系统和方法包括使用至少一个具有预定的降低驱动能力的驱动器，以可靠的检测算法来驱动存储器件的至少一个存储元件。与用于标准读取访问的驱动程序相比，至少一个驱动器具有降低的驱动能力。可靠的检测算法可以包括在从预期或期望的读取电流分歧的相应读取电流上检测故障存储器元件。

6. 发明授权

US07418699B2 Method and system for performing link-time code optimization without additional code analysis 失效
标题翻译：执行链路时代码优化的方法和系统，无需附加代码分析
公开(公告)号：US07418699B2
公开(公告)日：2008-08-26
申请号：US10784072
申请日：2004-02-20
申请人： Markus T. Metzger , Khem Raj , Oender Karpat , Robert Wiesner
发明人： Markus T. Metzger , Khem Raj , Oender Karpat , Robert Wiesner
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/54
摘要： A system for performing code optimization is described which includes an optimizing analyzer within a compiler to generate a first optimizing transformation and a second optimizing transformation and their satisfying conditions for a compiled code. An optimization transformation module is placed within a linker to determine which of the first and second optimizing transformations should be selected when the compiled code is linked with other compiled codes, and to execute the selected one of the first and second optimizing transformations at link-time. A method of performing code optimization is also described.
摘要翻译：描述了用于执行代码优化的系统，其包括编译器内的优化分析器以生成第一优化变换和第二优化变换及其对编译代码的满足条件。优化变换模块被放置在链接器内以确定当编译代码与其他编译代码相关联时应当选择第一和第二优化变换中的哪一个，并且在链接时执行第一和第二优化变换中选择的一个优化变换。还描述了执行代码优化的方法。

7. 发明申请

US20070143746A1 Method and system for efficient range and stride checking 有权
标题翻译：有效范围和步幅检查的方法和系统
公开(公告)号：US20070143746A1
公开(公告)日：2007-06-21
申请号：US11314225
申请日：2005-12-21
申请人： Markus Metzger , Robert Wiesner
发明人： Markus Metzger , Robert Wiesner
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/30
摘要： Embodiments of a method and system for compiling code, such as program-generated code, are disclosed herein. The method and system efficiently encode combined range and stride checks. For example, the method and system are operable to encode combined range and stride checks as they occur in a translation of switch statements. The method and system can generate code to perform the range and stride check, and to branch to the case body, if the range and stride checks are successful. The various embodiments may operate to provide an efficient code transformation, better code density, and processing performance. Other embodiments are described and claimed.
摘要翻译：本文公开了用于编译代码的方法和系统的实施例，例如程序生成的代码。该方法和系统有效地编码组合范围和步幅检查。例如，该方法和系统可操作用于在组合的范围和步幅检查在开关语句的翻译中发生时进行编码。方法和系统可以生成代码来执行范围和步幅检查，并且如果范围和步幅检查成功，则分支到案例主体。各种实施例可以操作以提供有效的代码转换，更好的代码密度和处理性能。描述和要求保护其他实施例。

8. 发明授权

US08649205B2 Memory cell, a method for forming a memory cell, and a method for operating a memory cell 有权
标题翻译：存储单元，用于形成存储单元的方法，以及用于操作存储单元的方法
公开(公告)号：US08649205B2
公开(公告)日：2014-02-11
申请号：US13370377
申请日：2012-02-10
申请人： Christian Peters , Mihail Jefremow , Jan Otterstedt , Wolf Allers , Robert Wiesner
发明人： Christian Peters , Mihail Jefremow , Jan Otterstedt , Wolf Allers , Robert Wiesner
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C11/16 , G11C2213/78
摘要： A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.
摘要翻译：提供存储单元，所述存储单元包括第一两端存储单元; 第二个两端存储元件; 控制器电路，被配置为将所述第一两端存储元件编程为一个或多个状态，将所述第二二端存储元件编程为一个或多个状态，其中，所述第一二端存储元件的状态和所述第二二端存储元件的状态终端记忆元素是相互依存的; 以及测量电路，被配置为测量与第一两端存储元件的状态相关联的第一两端存储元件信号与第二二端存储元件的状态相关的第二二端存储元件信号之间的差分信号记忆元素

9. 发明申请

US20130208527A1 MEMORY CELL, A METHOD FOR FORMING A MEMORY CELL, AND A METHOD FOR OPERATING A MEMORY CELL 有权
标题翻译：存储单元，形成存储单元的方法，以及操作存储单元的方法
公开(公告)号：US20130208527A1
公开(公告)日：2013-08-15
申请号：US13370377
申请日：2012-02-10
申请人： Christian Peters , Mihail Jefremow , Jan Otterstedt , Wolf Allers , Robert Wiesner
发明人： Christian Peters , Mihail Jefremow , Jan Otterstedt , Wolf Allers , Robert Wiesner
IPC分类号： G11C11/00 , G11C5/00 , G11C11/16
CPC分类号： G11C11/1673 , G11C11/16 , G11C2213/78
摘要： A memory cell is provided, the memory cell including a first two-terminal memory element; a second two-terminal memory element; a controller circuit configured to program the first two-terminal memory element to one or more states and the second two-terminal memory element to one or more states, wherein a state of the first two-terminal memory element and a state of the second two-terminal memory element are interdependent; and a measuring circuit configured to measure a difference signal between a first two-terminal memory element signal associated with the state of the first two-terminal memory element and a second two-terminal memory element signal associated with the state of the second two-terminal memory element.
摘要翻译：提供存储单元，所述存储单元包括第一两端存储单元; 第二个两端存储元件; 控制器电路，被配置为将所述第一两端存储元件编程为一个或多个状态，将所述第二二端存储元件编程为一个或多个状态，其中，所述第一二端存储元件的状态和所述第二二端存储元件的状态终端记忆元素是相互依存的; 以及测量电路，被配置为测量与第一两端存储元件的状态相关联的第一两端存储元件信号与第二二端存储元件的状态相关的第二二端存储元件信号之间的差分信号记忆元素

10. 发明授权

US08320191B2 Memory cell arrangement, method for controlling a memory cell, memory array and electronic device 有权
标题翻译：存储单元布置，用于控制存储单元的方法，存储器阵列和电子设备
公开(公告)号：US08320191B2
公开(公告)日：2012-11-27
申请号：US12049132
申请日：2008-03-14
申请人： Robert Strenz , Wolfram Langheinrich , Mayk Roehrich , Robert Wiesner
发明人： Robert Strenz , Wolfram Langheinrich , Mayk Roehrich , Robert Wiesner
IPC分类号： G11C16/04
CPC分类号： G11C16/0425 , G11C16/10 , H01L29/66825 , H01L29/7881
摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.
摘要翻译：在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除。

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