专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08552524B2 Semiconductor component with trench insulation and corresponding production method 有权
标题翻译：具有沟槽绝缘的半导体元件及相应的生产方法
公开(公告)号：US08552524B2
公开(公告)日：2013-10-08
申请号：US10523239
申请日：2003-07-19
申请人： Franz Schuler , Georg Tempel
发明人： Franz Schuler , Georg Tempel
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L21/763 , H01L21/76229 , H01L21/76232
摘要： The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation having a deep isolation trench with a covering insulation layer, a side wall insulation layer and an electrically conductive filling layer, which is electrically connected to a predetermined doping region of the semiconductor substrate in a bottom region of the trench. The use of a trench contact, which has a deep contact trench with a side wall insulation layer and an electrically conductive filling layer, which is likewise electrically connected to the predetermined doping region of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.
摘要翻译：本发明涉及具有沟槽隔离和相关制造方法的半导体部件，具有具有覆盖绝缘层的深隔离沟槽，侧壁绝缘层和导电填充层的沟槽隔离件，其电连接到预定的在沟槽的底部区域中的半导体衬底的掺杂区域。与接触沟槽的底部区域同样电连接到半导体衬底的预定掺杂区域的沟槽接触的使用，其具有与侧壁绝缘层和导电填充层的深接触沟槽，使得可以减小面积要求来改善电屏蔽性能。

2. 发明申请

US20110159661A1 Nonvolatile Memory Element and Production Method Thereof and Storage Memory Arrangement 有权
标题翻译：非易失性存储器元件及其生产方法和存储器存储器布置
公开(公告)号：US20110159661A1
公开(公告)日：2011-06-30
申请号：US13043129
申请日：2011-03-08
申请人： Laurent Breuil , Franz Schuler , Georg Tempel
发明人： Laurent Breuil , Franz Schuler , Georg Tempel
IPC分类号： H01L21/02
CPC分类号： H01L45/1608 , G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/33 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
摘要翻译：提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。场放大器结构是投影到切换材料中的电极的投影。存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

3. 发明授权

US07847325B2 Method of making discrete trap memory (DTM) mediated by fullerenes 有权
标题翻译：由富勒烯介导的离散陷阱记忆（DTM）的方法
公开(公告)号：US07847325B2
公开(公告)日：2010-12-07
申请号：US12403216
申请日：2009-03-12
申请人： Gerhard Poeppel , Georg Tempel
发明人： Gerhard Poeppel , Georg Tempel
IPC分类号： H01L29/76 , H01L29/788 , H01L21/02 , H01L51/00 , H01L29/68 , H01L21/04 , H01L21/336
CPC分类号： G11C13/025 , B82Y10/00 , G11C2216/06 , Y10S977/763 , Y10S977/773
摘要： A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.
摘要翻译：一种分立陷阱存储器，包括硅衬底层，硅衬底层上的底部氧化物层，底部氧化物层上的富勒烯层，富勒烯层上的顶部氧化物层和顶部氧化物层上的栅极层; 其中富勒烯层包含作为电荷阱的球形，椭圆形或内面的富勒烯。

4. 发明申请

US20080296662A1 Discrete Trap Memory (DTM) Mediated by Fullerenes 审中-公开
标题翻译：离散陷阱记忆（DTM）由富勒烯介导
公开(公告)号：US20080296662A1
公开(公告)日：2008-12-04
申请号：US11755509
申请日：2007-05-30
申请人： Gerhard Poeppel , Georg Tempel
发明人： Gerhard Poeppel , Georg Tempel
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： G11C13/025 , B82Y10/00 , G11C2216/06 , Y10S977/763 , Y10S977/773
摘要： A discrete trap memory, comprising a silicon substrate layer, a bottom oxide layer on the silicon substrate layer, a Fullerene layer on the bottom oxide layer, a top oxide layer on the Fullerene layer, and a gate layer on the top oxide layer; wherein the Fullerene layer comprises spherical, elliptical or endohedral Fullerenes that act as charge traps.
摘要翻译：一种分立陷阱存储器，包括硅衬底层，硅衬底层上的底部氧化物层，底部氧化物层上的富勒烯层，富勒烯层上的顶部氧化物层和顶部氧化物层上的栅极层; 其中富勒烯层包含作为电荷阱的球形，椭圆形或内面的富勒烯。

5. 发明申请

US20060226466A1 Non-volatile semiconductor memory element and corresponding production and operation method 有权
标题翻译：非易失性半导体存储器元件及相应的生产和操作方法
公开(公告)号：US20060226466A1
公开(公告)日：2006-10-12
申请号：US10524158
申请日：2003-08-08
申请人： Franz Schuler , Georg Tempel
发明人： Franz Schuler , Georg Tempel
IPC分类号： H01L29/788
CPC分类号： H01L29/66833 , G11C16/0475 , H01L21/28282 , H01L29/7923
摘要： The invention relates to a nonvolatile semiconductor storage element and an associated production and control method, comprising a semiconductor substrate (1) in which a source region (S), a drain region (D) and an intermediate channel region are formed. On a first part section (I) of the channel region, a control layer (5) is formed and insulated from the channel region by a first insulating layer (2A) whereas respective charge storage layers (3A and 3B) are formed in a second part section (IIA, IIB) of the channel region and are insulated from the channel region by a second insulating layer (2BA and 2BB). On the charge storage layer (3A, 3B), a programming layer (6A, 6B) is formed and insulated from that by a third insulating layer (4A, 4B) and is electrically connected to a respective source region (S) and drain region (D) via a respective interconnect layer (6AA, 6BB).
摘要翻译：本发明涉及一种非易失性半导体存储元件及相关的制造和控制方法，包括其中形成源极区（S），漏极区（D）和中间沟道区的半导体衬底（1）。在沟道区的第一部分（I）上，通过第一绝缘层（2A）形成控制层（5）并与沟道区绝缘，而形成各自的电荷存储层（3A和3B）在沟道区域的第二部分部分（IIA，IIB）中，并且通过第二绝缘层（2 BA和2BB）与沟道区域绝缘。在电荷存储层（3A，3B）上，编程层（6A，6B）与第三绝缘层（4A，4B）的编程层（6A，6B）形成绝缘，并与第一绝缘层（6A，6BB）中的至少一个（S）和漏极区（D）。

6. 发明申请

US20060131637A1 Bit line structure and production method thereof 有权
标题翻译：位线结构及其制造方法
公开(公告)号：US20060131637A1
公开(公告)日：2006-06-22
申请号：US11273668
申请日：2005-11-14
申请人： Ronald Kakoschke , Franz Schuler , Georg Tempel
发明人： Ronald Kakoschke , Franz Schuler , Georg Tempel
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.
摘要翻译：本公开涉及位线结构和相关联的位线结构的制造方法。在位线结构中，至少在第二触点的区域和与其相邻的多个第一触点的区域中，隔离沟槽填充有导电沟槽填充层。隔离沟槽连接到与第二接触相邻的第一掺杂区域，以实现埋地接触旁路线路。

7. 发明申请

US20060108692A1 Bit line structure and method for the production thereof 有权
标题翻译：位线结构及其制造方法
公开(公告)号：US20060108692A1
公开(公告)日：2006-05-25
申请号：US11273595
申请日：2005-11-14
申请人： Ronald Kakoschke , Franz Schuler , Georg Tempel
发明人： Ronald Kakoschke , Franz Schuler , Georg Tempel
IPC分类号： H01L23/52
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.
摘要翻译：为半导体元件或电路布置提供了位线结构和相关联的制造方法。位线结构包含表面位线和掩埋位线。掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

8. 发明申请

US20060097238A1 Non-volatile memory element and production method thereof and storage memory arrangement 有权
标题翻译：非易失性存储元件及其制造方法和存储存储器装置
公开(公告)号：US20060097238A1
公开(公告)日：2006-05-11
申请号：US10522386
申请日：2003-07-19
申请人： Laurent Breuil , Franz Schuler , Georg Tempel
发明人： Laurent Breuil , Franz Schuler , Georg Tempel
IPC分类号： H01L47/00
CPC分类号： H01L45/1608 , G11C13/0011 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/33 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/148 , H01L45/149 , H01L45/16
摘要： A nonvolatile memory element and to associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.
摘要翻译：提出了一种非易失性存储器元件以及相关联的制造方法和存储元件布置。非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。场放大器结构是投影到切换材料中的电极的投影。存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

9. 发明授权

US6083765A Method for producing semiconductor memory device having a capacitor 失效
标题翻译：一种具有电容器的半导体存储器件的制造方法
公开(公告)号：US6083765A
公开(公告)日：2000-07-04
申请号：US135623
申请日：1998-08-18
申请人： Georg Tempel
发明人： Georg Tempel
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11507 , H01L27/10808 , H01L27/11502 , H01L28/55
摘要： A semiconductor memory device includes a semiconductor substrate having a surface defining a plane extending substantially parallel thereto. A multiplicity of memory cells disposed on the substrate each have a selection transistor disposed in the plane. The transistor has a gate terminal and first and second electrode terminals. Each of the memory cells has a storage capacitor associated with and triggerable by the transistor. The capacitor has a ferroelectric dielectric and first and second capacitor electrodes. The capacitor has a configuration projecting upward from the plane and is disposed inside a trench extending as far as the second electrode terminal of the transistor. A word line is connected to the gate terminal of the transistor, a bit line is connect to the first electrode terminal of the transistor, and a common conductor layer of electrically conductive material is connected to the first capacitor electrode of the capacitor. A method for producing the device includes producing the capacitor after production of the transistor and metallizing layers associated with the transistor for connection of the word and bit lines, in a configuration projecting upward from the plane, and placing the capacitor inside a trench extending as far as the second electrode terminal of the transistor.
摘要翻译：半导体存储器件包括具有限定基本上平行延伸的平面的表面的半导体衬底。设置在基板上的多个存储单元各自具有设置在平面中的选择晶体管。晶体管具有栅极端子和第一和第二电极端子。每个存储单元具有与晶体管相关联并且可由晶体管触发的存储电容器。电容器具有铁电介质和第一和第二电容器电极。电容器具有从平面向上突出的配置，并且设置在延伸到晶体管的第二电极端子的沟槽内。字线连接到晶体管的栅极端子，位线连接到晶体管的第一电极端子，并且导电材料的公共导体层连接到电容器的第一电容器电极。一种制造该器件的方法包括：在从晶体管向上突出的结构中制造晶体管和与用于连接字线和位线的晶体管相连的金属化层的电容器，以及将电容器放置在远延伸的沟槽内作为晶体管的第二电极端子。

10. 发明授权

US5925905A MOS circuit configuration for switching high voltages on a semiconductor chip 失效
标题翻译：用于在半导体芯片上切换高电压的MOS电路配置
公开(公告)号：US5925905A
公开(公告)日：1999-07-20
申请号：US899746
申请日：1997-07-24
申请人： Armin Hanneberg , Georg Tempel
发明人： Armin Hanneberg , Georg Tempel
IPC分类号： G11C16/06 , G11C5/14 , G11C16/12 , G11C16/14 , H03K3/356 , H03K17/10 , H03K17/693 , H01L29/772
CPC分类号： G11C5/143 , G11C16/12 , G11C16/14 , G11C5/14 , H03K17/102 , H03K17/693 , H03K3/356017 , H03K3/356147
摘要： The MOS circuit configuration allows switching high voltages on a semiconductor chip. In order to switch a high negative voltage, for example as a programming voltage on the word line of a flash-memory, two circuit variants are given which are formed only with transistors of the same conductivity type as the substrate. The substrate and the transistors formed in the well are p-conductive. In this way it is possible to dispense with deep insulating wells which require special technology.
摘要翻译： MOS电路配置允许在半导体芯片上切换高电压。为了切换高负电压，例如作为闪速存储器的字线上的编程电压，给出了仅由与衬底相同导电类型的晶体管形成的两个电路变型。形成在阱中的衬底和晶体管是p导电的。以这种方式，可以省去需要特殊技术的深层绝缘井。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式