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1. 发明申请

US20130258758A1 Single Cycle Data Copy for Two-Port SRAM 有权
标题翻译：双端口SRAM的单周期数据复制
公开(公告)号：US20130258758A1
公开(公告)日：2013-10-03
申请号：US13435828
申请日：2012-03-30
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： G11C11/00 , G06F17/50
CPC分类号： G06F17/505 , G11C11/412 , G11C11/419
摘要： A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.
摘要翻译：静态随机存取存储器（SRAM）包括一列SRAM存储单元。 SRAM可以包括电路，用于将存储在SRAM存储器单元的列中的任何SRAM存储器单元中的值复制到SRAM的单个周期中的SRAM存储单元列中的任何SRAM存储器单元。

2. 发明申请

US20130222031A1 IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE 有权
标题翻译：实现节能自卸机构结构
公开(公告)号：US20130222031A1
公开(公告)日：2013-08-29
申请号：US13404096
申请日：2012-02-24
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
IPC分类号： H03K3/289
CPC分类号： H03K3/012 , H03K3/0375
摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.
摘要翻译：一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。主从锁存器包括虚拟电源连接。至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。

3. 发明授权

US08395963B2 Data security for dynamic random access memory at power-up 失效
标题翻译：上电时动态随机存取存储器的数据安全
公开(公告)号：US08395963B2
公开(公告)日：2013-03-12
申请号：US12963965
申请日：2010-12-09
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： G11C8/00
CPC分类号： G11C11/4072
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by driving the wordlines of all the cells to an activated state. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value. In a preferred embodiment, the wordlines are all turned on simultaneously during a power on reset period. Preferably a power on reset signal is used to drive each logic gate of the pre-decoder portion of the address decoder in order to assert all the wordlines.
摘要翻译：电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。通过将所有单元的字线驱动到激活状态，同时通过接通DRAM存储单元的晶体管来擦除所有的DRAM存储单元。当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。在优选实施例中，在上电复位周期期间，字线都同时导通。优选地，上电复位信号用于驱动地址解码器的预解码器部分的每个逻辑门，以便断言所有字线。

4. 发明申请

US20110109366A1 Method and Apparatus to Limit Circuit Delay Dependence on Voltage for Single Phase Transition 失效
标题翻译：限制电路延迟依赖于单相转换电压的方法和装置
公开(公告)号：US20110109366A1
公开(公告)日：2011-05-12
申请号：US12613673
申请日：2009-11-06
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： H03H11/26
CPC分类号： H03K5/1534 , H03K5/133
摘要： A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.
摘要翻译：延迟电路接收具有输入转变的数据输入并产生具有输出转变的数据输出。延迟电路由具有电压的电压源供电。第一延迟元件被配置为产生第一数据信号，其中第一边缘相对于输入转换具有相对恒定的延迟，而与电压源的电压无关。第二延迟元件被配置为产生具有作为电压源的电压的函数的相对于输入转变的延迟的第二边缘的第二数据信号。选择元件使得数据输出处的输出转变对应于第一边缘和第二边缘中最新选择的一个。延迟电路可以用在脉冲发生电路中。

5. 发明申请

US20090271669A1 High-Speed Testing of Integrated Devices 有权
标题翻译：集成器件的高速测试
公开(公告)号：US20090271669A1
公开(公告)日：2009-10-29
申请号：US12110955
申请日：2008-04-28
申请人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Travis R. Hebig
发明人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Travis R. Hebig
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/48 , G11C11/41 , G11C29/12 , G11C29/1201 , G11C29/50012 , G11C2029/0401
摘要： A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
摘要翻译：一种用于允许具有用于存储数据的存储器单元的具有核的存储器件的高速可测试性的方法，包括：使得具有来自所述核的第一逻辑状态或第二逻辑状态的数据信号到达所述存储器件的输出端口在功能操作模式的评估周期内，并且在LBIST模式期间通过内置自检的阵列; 使得数据信号在LBIST模式期间能够在LBIST模式期间从与核心的数据信号在功能操作模式期间到达评估周期内的读取输出端口的最新可能时间一致的时刻改变为第一逻辑状态并通过自检内置的数组; 以及执行被配置为测试位于所述存储器件的传输路径下游的逻辑块的逻辑内置自检。

6. 发明授权

US07502276B1 Method and apparatus for multi-word write in domino read SRAMs 失效
标题翻译：在多米诺骨牌SRAM中多字写入的方法和装置
公开(公告)号：US07502276B1
公开(公告)日：2009-03-10
申请号：US12122185
申请日：2008-05-16
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： G11C8/12 , G11C11/413 , G11C8/10 , G11C29/18 , G11C29/26
CPC分类号： G11C8/10 , G11C11/413 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A domino read SRAM capable of writing multiple wordlines simultaneously. A read/write multiplexer may allow conventional, single-wordline selection during a read operation, while allowing external logic, such as an ABIST controller, to enable multiple wordlines during a write operation.
摘要翻译：一个能够同时写入多个字线的多米诺骨牌SRAM。读/写复用器可以允许在读取操作期间的常规的单字线选择，同时允许诸如ABIST控制器的外部逻辑在写操作期间启用多个字线。

7. 发明授权

US08669800B2 Implementing power saving self powering down latch structure 有权
标题翻译：实现节能自卸锁结构
公开(公告)号：US08669800B2
公开(公告)日：2014-03-11
申请号：US13404096
申请日：2012-02-24
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
IPC分类号： H03K3/289
CPC分类号： H03K3/012 , H03K3/0375
摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.
摘要翻译：一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。主从锁存器包括虚拟电源连接。至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。

8. 发明申请

US20130235681A1 IMPLEMENTING RC AND COUPLING DELAY CORRECTION FOR SRAM 有权
标题翻译：实现SRAM的RC和耦合延迟校正
公开(公告)号：US20130235681A1
公开(公告)日：2013-09-12
申请号：US13414133
申请日：2012-03-07
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： G11C7/12 , G06F17/50
CPC分类号： G11C7/12 , G11C11/419
摘要： A method and circuit for implementing delay correction in static random access memory (SRAM), and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a precharge enable signal coupled between precharge near and precharge far signals and wordline near and wordline far signals of the SRAM. A precharge pull down device is coupled between the precharge far signal and ground and is controlled responsive to the precharge enable signal to decrease a time delay of the falling transition of the precharge far signal. A respective word line pull up device is coupled between a respective wordline far signal and a voltage supply rail and is controlled responsive to the precharge enable signal to increase wordline voltage level upon a rising transition of the wordline far signal.
摘要翻译：一种用于实现静态随机存取存储器（SRAM）中的延迟校正的方法和电路，以及设置有被摄体电路所在的设计结构。 SRAM电路包括预充电接近和预充电远信号以及SRAM的字线附近和字线远信号之间的预充电使能信号。预充电下拉装置耦合在预充电远信号和地之间，并且响应于预充电使能信号被控制以减小预充电远信号的下降转换的时间延迟。相应的字线上拉器件耦合在相应的字线远信号和电压供应轨之间，并且响应于预充电使能信号被控制，以在字线远信号的上升转变时增加字线电压电平。

9. 发明授权

US08520429B2 Data dependent SRAM write assist 有权
标题翻译：数据依赖SRAM写入辅助
公开(公告)号：US08520429B2
公开(公告)日：2013-08-27
申请号：US13101436
申请日：2011-05-05
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/413
摘要： A semiconductor chip has an SRAM (static random access memory). The SRAM includes a data dependent write assist circuit which, on writes, reduces a supply voltage on one of a cross coupled inverter pair in an SRAM cell, thereby making it easier to overcome the one of the cross coupled inverters.
摘要翻译：半导体芯片具有SRAM（静态随机存取存储器）。 SRAM包括数据相关写入辅助电路，其在写入时降低SRAM单元中的交叉耦合的反相器对中的一个上的电源电压，从而使得更容易克服交叉耦合的反相器之一。

10. 发明申请

US20120233576A1 SCHEMATIC-BASED LAYOUT MIGRATION 审中-公开
标题翻译：基于模式的布局迁移
公开(公告)号：US20120233576A1
公开(公告)日：2012-09-13
申请号：US13043761
申请日：2011-03-09
申请人： Geoffrey R. Barrows , Derick G. Behrends , William J. Craig , Michael S. Gray , Matthew T. Guzowski , Kevin W. McCullen , Rani Narayan , Robert F. Walker
发明人： Geoffrey R. Barrows , Derick G. Behrends , William J. Craig , Michael S. Gray , Matthew T. Guzowski , Kevin W. McCullen , Rani Narayan , Robert F. Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells.
摘要翻译：方法，系统，计算机等实施例将原始集成电路设计接收到计算机化设备中。本文中的方法使用计算机化设备自动地用原始集成电路设计中的至少一些原始单元替换替换单元。每个替换单元格具有与任何特定设计尺寸无关的初始单元格大小。这里的方法将集成电路设计的原始设计尺寸自动地改变为改变的设计尺寸，并且将每个替换单元的初始单元尺寸自动地单独地改变为不同的尺寸。基于每个替换单元的改变的设计尺寸中所需的不同的空间量，将至少两个不同的替换单元从初始单元大小改变为不同的尺寸减小量。

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