专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160126184A1 DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
公开(公告)号：US20160126184A1
公开(公告)日：2016-05-05
申请号：US14931175
申请日：2015-11-03
申请人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
发明人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
IPC分类号： H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L21/76879 , H01L21/76883 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

2. 发明申请

US20160104642A1 SELF-ALIGNED VIA AND PLUG PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
公开(公告)号：US20160104642A1
公开(公告)日：2016-04-14
申请号：US14965734
申请日：2015-12-10
申请人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
发明人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
IPC分类号： H01L21/768
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

3. 发明授权

US09209077B2 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects 有权
标题翻译：对角线硬掩模，用于在制造后端线（BEOL）互连中改进覆盖层
公开(公告)号：US09209077B2
公开(公告)日：2015-12-08
申请号：US14137588
申请日：2013-12-20
申请人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
发明人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
IPC分类号： H01L21/768 , H01L21/033 , H01L21/311 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L21/76879 , H01L21/76883 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.
摘要翻译：描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。该方法还涉及在第一硬掩模层之上形成第二硬掩模层。第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。蚀刻涉及去除一个或多个牺牲材料的一部分。

4. 发明申请

US20140203400A1 METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES 有权
标题翻译：金属绝缘体 - 金属电容器形成技术
公开(公告)号：US20140203400A1
公开(公告)日：2014-07-24
申请号：US13748277
申请日：2013-01-23
申请人： Mauro J. Kobrinsky , Robert L. Bristol , Michael C. Mayberry
发明人： Mauro J. Kobrinsky , Robert L. Bristol , Michael C. Mayberry
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L21/0337 , H01L27/224 , H01L28/82
摘要： Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.
摘要翻译：公开了用于提供具有大体波形轮廓的MIM电容器的技术和结构。使用牺牲性自组织材料提供波纹形状，其有效地产生响应于被形成MIM电容器的介电材料的处理（热或其它合适的刺激）的图案。自组织材料可以是例如响应于热或其它刺激而分离成两个交替相的定向自组装材料层，其中相中的一个相可以相对于另一相被选择性地蚀刻到提供所需的图案。在另一个例子中，自组织材料是在加热时聚结成孤岛的材料层。根据本公开将会理解，所公开的技术可以用于例如增加每单位面积的电容，其可以通过蚀刻更深的电容器沟槽/孔来缩放。

5. 发明申请

US20160172237A1 NON-LITHOGRAPHICALLY PATTERNED DIRECTED SELF ASSEMBLY ALIGNMENT PROMOTION LAYERS 有权
公开(公告)号：US20160172237A1
公开(公告)日：2016-06-16
申请号：US14778562
申请日：2013-06-27
申请人： Robert L. Bristol , Rami HOURANI , Eungnak HAN , James M. BLACKWELL
发明人： Robert L. Bristol , Rami HOURANI , Eungnak HAN , James M. BLACKWELL
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L21/02 , H01L21/311
CPC分类号： H01L21/76897 , B81C1/00031 , B81C2201/0149 , H01L21/02118 , H01L21/0271 , H01L21/31051 , H01L21/31127 , H01L21/76822 , H01L21/76834 , H01L23/528 , H01L23/5328 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

6. 发明授权

US09236342B2 Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects 有权
标题翻译：自对准通孔和插头图案化，用于后端（BEOL）互连的光触点
公开(公告)号：US09236342B2
公开(公告)日：2016-01-12
申请号：US14133385
申请日：2013-12-18
申请人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
发明人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
IPC分类号： H01L21/311 , H01L23/522 , H01L21/768 , H01L21/027 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.
摘要翻译：描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。介质线具有高于金属线的最上表面的最上表面。集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。介质线具有比第二光栅的金属线的最下表面低的最低表面。第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中第二光栅的线。介电材料的区域由交联的可光致发光材料组成。

7. 发明申请

US20150170926A1 DIELECTRIC LAYERS HAVING ORDERED ELONGATE PORES 审中-公开
标题翻译：具有订购的ELONGATE PORES的电介质层
公开(公告)号：US20150170926A1
公开(公告)日：2015-06-18
申请号：US14108255
申请日：2013-12-16
申请人： David J. Michalak , Robert L. Bristol , Arkaprabha Sengupta , Mauro J. Kobrinsky
发明人： David J. Michalak , Robert L. Bristol , Arkaprabha Sengupta , Mauro J. Kobrinsky
IPC分类号： H01L21/308 , H01L23/50 , H01L21/311
CPC分类号： H01L23/50 , H01L21/02203 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/233 , Y10T428/249975 , H01L2924/00
摘要： Embodiments of the present disclosure describe dielectric layers and methods for their fabrication and use. In some embodiments, a dielectric layer may include a dielectric material and a plurality of elongate pores. The dielectric material may have a first surface and an opposing second surface spaced away from the first surface in a direction defined by an axis, and may have a Young's modulus (E0) in the direction defined by the axis. Individual elongate pores of the plurality of elongate pores may extend from the second surface with a longitudinal axis substantially parallel to the axis. The plurality of elongate pores may provide the dielectric layer with a porosity, p, greater than approximately 30%, and the dielectric layer may have a Young's modulus approximately equal to E0*(1−p) in the direction defined by the axis. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于其制造和使用的电介质层及其方法。在一些实施例中，电介质层可以包括电介质材料和多个细长孔。电介质材料可以具有在由轴线限定的方向上与第一表面隔开的第一表面和相对的第二表面，并且可以在由轴限定的方向上具有杨氏模量（E0）。多个细长孔中的单个细长孔可以从第二表面延伸，其纵轴基本上平行于该轴。多个细长的孔可以提供介电层具有大于约30％的孔隙率p，并且电介质层可以具有在由轴限定的方向上大约等于E0 *（1-p）的杨氏模量。可以描述和/或要求保护其他实施例。

8. 发明授权

US07825424B2 Methods to manufacture contaminant-gettering materials in the surface of EUV optics 有权
标题翻译：在EUV光学表面制造污染物吸收材料的方法
公开(公告)号：US07825424B2
公开(公告)日：2010-11-02
申请号：US12002152
申请日：2007-12-14
申请人： Robert L. Bristol , Bruce H. Billett
发明人： Robert L. Bristol , Bruce H. Billett
IPC分类号： H01L29/26
CPC分类号： G21K1/06 , G21K2201/067
摘要： Methods to manufacture contaminant-gettering materials in the surface of EUV optics are described herein. An optical element is patterned and a contaminant-gettering material is formed on a surface of the optical element. In one embodiment, a photoresist is deposited on an optical coating on the optical element. Trenches are formed in the optical coating. The gettering agent is formed into the trenches over the photoresist. Next, the photoresist is removed from the optical coating to expose the gettering agent in the trenches. For another embodiment, patches of a nanotube forest having a gettering agent are formed in designated areas of an optical element. The gettering agent of the patches may be a plurality of carbon nanotubes. The optical coating is formed on a substrate between patches of the gettering agent.
摘要翻译：本文描述了在EUV光学器件的表面中制造污染物吸收材料的方法。对光学元件进行图案化，并且在光学元件的表面上形成污染物吸收材料。在一个实施例中，光致抗蚀剂沉积在光学元件上的光学涂层上。在光学涂层中形成沟槽。吸光剂形成在光致抗蚀剂上的沟槽中。接下来，从光学涂层去除光致抗蚀剂以暴露沟槽中的吸杂剂。对于另一个实施例，在光学元件的指定区域中形成具有吸气剂的纳米管森林的贴片。补片的吸气剂可以是多个碳纳米管。该光学涂层形成在吸气剂的贴片之间的衬底上。

9. 发明授权

US09548269B2 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects 有权
标题翻译：对角线硬掩模，用于在制造后端线（BEOL）互连中改进覆盖层
公开(公告)号：US09548269B2
公开(公告)日：2017-01-17
申请号：US14931175
申请日：2015-11-03
申请人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
发明人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
IPC分类号： H01L29/40 , H01L23/522 , H01L21/768 , H01L21/033 , H01L23/528 , H01L21/311
CPC分类号： H01L23/5226 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L21/76879 , H01L21/76883 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.
摘要翻译：描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅并且包括与第一光栅交错的一个或多个牺牲材料。该方法还涉及在第一硬掩模层之上形成第二硬掩模层。第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。蚀刻涉及去除一个或多个牺牲材料的一部分。

10. 发明申请

US20150179513A1 DIAGONAL HARDMASKS FOR IMPROVED OVERLAY IN FABRICATING BACK END OF LINE (BEOL) INTERCONNECTS 有权
标题翻译：用于改进线路（BEOL）互连的后端改进的对角线
公开(公告)号：US20150179513A1
公开(公告)日：2015-06-25
申请号：US14137588
申请日：2013-12-20
申请人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
发明人： Alan M. Myers , Kanwal Jit Singh , Robert L. Bristol , Jasmeet S. Chawla
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L21/033
CPC分类号： H01L23/5226 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76816 , H01L21/76879 , H01L21/76883 , H01L21/76897 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.
摘要翻译：描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。该方法还涉及在第一硬掩模层之上形成第二硬掩模层。第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。蚀刻涉及去除一个或多个牺牲材料的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式