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1. 发明公开

US20230207551A1 STANDARD CELL ARCHITECTURE WITHOUT POWER DELIVERY SPACE ALLOCATION 审中-公开
公开(公告)号：US20230207551A1
公开(公告)日：2023-06-29
申请号：US17561693
申请日：2021-12-23
申请人： Sukru YEMENICIOGLU , Richard E. SCHENKER , Xinning WANG , Mauro J. KOBRINSKY , Tahir GHANI
发明人： Sukru YEMENICIOGLU , Richard E. SCHENKER , Xinning WANG , Mauro J. KOBRINSKY , Tahir GHANI
IPC分类号： H01L27/02 , H01L23/522 , G06F30/394
CPC分类号： H01L27/0207 , H01L23/5226 , G06F30/394
摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. Other embodiments may be described or claimed.

2. 发明申请

US20160104642A1 SELF-ALIGNED VIA AND PLUG PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS 审中-公开
公开(公告)号：US20160104642A1
公开(公告)日：2016-04-14
申请号：US14965734
申请日：2015-12-10
申请人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
发明人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
IPC分类号： H01L21/768
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

3. 发明授权

US09236342B2 Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects 有权
标题翻译：自对准通孔和插头图案化，用于后端（BEOL）互连的光触点
公开(公告)号：US09236342B2
公开(公告)日：2016-01-12
申请号：US14133385
申请日：2013-12-18
申请人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
发明人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
IPC分类号： H01L21/311 , H01L23/522 , H01L21/768 , H01L21/027 , H01L23/532
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.
摘要翻译：描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。介质线具有高于金属线的最上表面的最上表面。集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。介质线具有比第二光栅的金属线的最下表面低的最低表面。第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中第二光栅的线。介电材料的区域由交联的可光致发光材料组成。

4. 发明申请

US20150171010A1 SELF-ALIGNED VIA AND PLUG PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS 有权
标题翻译：自动对准通过与背光源（BEOL）互连的光电放大器
公开(公告)号：US20150171010A1
公开(公告)日：2015-06-18
申请号：US14133385
申请日：2013-12-18
申请人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
发明人： Robert L. Bristol , Kevin Lin , Kanwal Jit Singh , Alan M. Myers , Richard E. Schenker
IPC分类号： H01L23/522 , H01L21/027 , H01L21/311 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/0274 , H01L21/31111 , H01L21/31144 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/76825 , H01L23/522 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.
摘要翻译：描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。介质线具有高于金属线的最上表面的最上表面。集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。介质线具有比第二光栅的金属线的最下表面低的最低表面。第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中第二光栅的线。介电材料的区域由交联的可光致发光材料组成。

5. 发明申请

US20150091174A1 METHODS OF FORMING PARALLEL WIRES OF DIFFERENT METAL MATERIALS THROUGH DOUBLE PATTERNING AND FILL TECHNIQUES 有权
标题翻译：通过双重图案和填充技术形成不同金属材料的平行线的方法
公开(公告)号：US20150091174A1
公开(公告)日：2015-04-02
申请号：US14040191
申请日：2013-09-27
申请人： James S. Clarke , Anthony C. Schmitz , Richard E. Schenker
发明人： James S. Clarke , Anthony C. Schmitz , Richard E. Schenker
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76816 , H01L21/76834 , H01L21/76838 , H01L21/76879 , H01L21/76883 , H01L21/76897 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.
摘要翻译：一种集成电路和形成集成电路的方法，该集成电路包括包括表面的第一介电层，限定在电介质层表面中的多个第一沟槽和多个第一布线，其中，每个第一布线形成在第一个沟渠。集成电路还包括限定在电介质层表面中的多个第二沟槽和多个第二布线，其中每个第二布线形成在每个第二沟槽中。此外，第一导线包括具有第一体电阻率的第一材料，并且第二导线包括具有第二体电阻率的第二材料，其中第一体电阻率和第二体电阻率不同。

6. 发明申请

US20150214094A1 METHODS FOR FORMING INTERCONNECT LAYERS HAVING TIGHT PITCH INTERCONNECT STRUCTURES 有权
标题翻译：用于形成具有紧密间距互连结构的互连层的方法
公开(公告)号：US20150214094A1
公开(公告)日：2015-07-30
申请号：US14163323
申请日：2014-01-24
申请人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
发明人： Christopher J. Jezewski , Jasmeet S. Chawla , Kanwal Jit Singh , Alan M. Myers , Elliot N. Tan , Richard E. Schenker
IPC分类号： H01L21/768
CPC分类号： H01L21/7688 , H01L21/0337 , H01L21/31144 , H01L21/76808 , H01L21/76811 , H01L21/76816 , H01L21/76831 , H01L21/76886 , H01L21/76897 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.
摘要翻译：用于形成在电介质层内具有紧密间距互连结构的互连层的工艺，其中用于形成的互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的电位。本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

7. 发明授权

US06428936B1 Method and apparatus that compensates for phase shift mask manufacturing defects 有权
标题翻译：补偿相移掩模制造缺陷的方法和装置
公开(公告)号：US06428936B1
公开(公告)日：2002-08-06
申请号：US09465520
申请日：1999-12-16
申请人： Richard E. Schenker
发明人： Richard E. Schenker
IPC分类号： G03F900
CPC分类号： G03F1/30
摘要： An apparatus is described comprising a phase shift mask having a transparent region. The transparent region comprises an etched region of a transparent layer. The etched region has a final etch depth that corresponds to a designed for phase shift and the designed for phase shift is greater than 180°.
摘要翻译：描述了一种包括具有透明区域的相移掩模的装置。透明区域包括透明层的蚀刻区域。蚀刻区域具有对应于设计用于相移的最终蚀刻深度，并且设计为相移大于180°。

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