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1. 发明授权

US08843776B2 Method and system of reporting electrical current to a processor 有权
标题翻译：向处理器报告电流的方法和系统
公开(公告)号：US08843776B2
公开(公告)日：2014-09-23
申请号：US13147429
申请日：2009-02-27
申请人： Eugene M. Dvoskin , Noel D. Scott , Robert J. Horning
发明人： Eugene M. Dvoskin , Noel D. Scott , Robert J. Horning
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26
摘要： Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn.
摘要翻译：向处理器报告电流。示例性实施例中的至少一些是包括以计算机系统的处理器指示的电压向处理器提供操作功率的方法，测量由处理器实际绘制的电流，并向处理器报告由该处理器绘制的电流值处理器。报告的电流值实际上与实际绘制的电流的测量误差大于实际绘制的电流值。

2. 发明申请

US20130173901A1 MULTI-PROCESSOR COMPUTER SYSTEMS AND METHODS 审中-公开
标题翻译：多处理器计算机系统和方法
公开(公告)号：US20130173901A1
公开(公告)日：2013-07-04
申请号：US13821506
申请日：2010-11-01
申请人： Raphael Gay , Robert J. Horning
发明人： Raphael Gay , Robert J. Horning
IPC分类号： G06F9/44
CPC分类号： G06F9/4405 , G06F13/12 , G06F13/4068
摘要： Multi-processor computer systems and methods are provided. A multi-processor computer system can include a plurality of communicatively coupled processors (1101-N), each coupled to a common motherboard (120) and each associated with a memory (1401-N). The system can include a boot code (130) executable from at least one of a standard mode and an independent mode. The plurality of communicatively coupled processors can execute one instance of the boot code in standard mode and at least a portion of the plurality of communicatively coupled processors can execute one instance of the boot code in independent mode.
摘要翻译：提供多处理器计算机系统和方法。多处理器计算机系统可以包括多个通信耦合处理器（1101-N），每个处理器耦合到公共母板（120），并且每个处理器与存储器（1401-N）相关联。该系统可以包括可从标准模式和独立模式中的至少一个执行的引导代码（130）。多个通信耦合的处理器可以以标准模式执行引导代码的一个实例，并且多个通信耦合的处理器的至少一部分可以以独立模式执行引导代码的一个实例。

3. 发明授权

US06542968B1 System and method for managing data in an I/O cache 失效
标题翻译：用于管理I / O缓存中的数据的系统和方法
公开(公告)号：US06542968B1
公开(公告)日：2003-04-01
申请号：US09232293
申请日：1999-01-15
申请人： Thomas V Spencer , Robert J Horning
发明人： Thomas V Spencer , Robert J Horning
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F12/0862 , G06F2212/6028
摘要： The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.
摘要翻译：本发明一般涉及一种系统和方法，用于经由I / O高速缓存将数据从系统存储器提取到与PCI总线通信的设备。概括地说，本发明可以被看作是传达某些提取提示的新颖方式; 即指定要从系统内存中提取的数据的某些质量的提示。在操作中，I / O缓存可以使用这样的提示来更有效地管理通过它的数据。作为一个例子，如果基于提示，I / O缓存的控制器知道（或假设）所取出的数据是ATM数据，则它也将精确地知道（基于ATM数据的性质），将48个字节的数据有效载荷发送到请求设备，并且I / O缓存可以精确地预取这一数量的数据（通常为一个或两个高速缓存行）。根据本发明的一个方面，这种系统包括插入在系统存储器和PCI总线之间的输入/输出（I / O）高速缓冲存储器，其中高速缓冲存储器具有多个数据形式的内部存储器空间高速缓存中的行。该系统还包括用于每个PCI主机的多个寄存器，其被配置为定义提取准则。最后，该系统包括一个寄存器选择器，被配置为在多个寄存器中选择一个活动寄存器，其中由该寄存器指定该设备的取得标准。

4. 发明授权

US5416918A Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers 失效
标题翻译：低偏移系统，用于通过将外部时钟片外到外部延迟元件，然后反馈到片上驱动器进行接口连接
公开(公告)号：US5416918A
公开(公告)日：1995-05-16
申请号：US187264
申请日：1994-01-27
申请人： Craig A. Gleason , Robert J. Horning
发明人： Craig A. Gleason , Robert J. Horning
IPC分类号： G06F1/10 , G06F1/04
CPC分类号： G06F1/10
摘要： A low skew interface system for enabling an ASIC chip's receivers to latch information from one or more buses. The interface comprises a driver circuit connected to an internal clock of the chip for generating another clock signal with phase different from the phase of the internal clock. A delay element is located off the chip and connected to the driver circuit for delaying the clock signal, thereby generating a latch clock signal. The latch clock signal is sent back on-chip to enable the receivers to transfer information from one of the buses to the chip.
摘要翻译：低偏移接口系统，用于使ASIC芯片的接收器能够锁存来自一个或多个总线的信息。该接口包括连接到芯片的内部时钟的驱动器电路，用于产生具有不同于内部时钟的相位的相位的另一个时钟信号。延迟元件位于芯片外并连接到驱动器电路，用于延迟时钟信号，从而产生锁存时钟信号。锁存时钟信号在芯片上被送回，以使接收器能够将信息从一个总线传送到芯片。

5. 发明申请

US20110289337A1 Method And System Of Reporting Electrical Current To A Processor 有权
标题翻译：向处理器报告电流的方法和系统
公开(公告)号：US20110289337A1
公开(公告)日：2011-11-24
申请号：US13147429
申请日：2009-02-27
申请人： Eugene M. Dvoskin , Noel D. Scott , Robert J. Horning
发明人： Eugene M. Dvoskin , Noel D. Scott , Robert J. Horning
IPC分类号： G06F1/28
CPC分类号： G06F1/26
摘要： Reporting electrical current to a processor. At least some of the illustrative embodiments are methods including providing operational power to a processor at a voltage indicated by the processor of a computer system, measuring electrical current actually drawn by the processor, and reporting to the processor a value of electrical current drawn by the processor. The value of electrical current reported different than the electrical current actually drawn by more than a measurement error of measuring the electrical current actually drawn.
摘要翻译：向处理器报告电流。示例性实施例中的至少一些是包括以计算机系统的处理器指示的电压向处理器提供操作功率的方法，测量由处理器实际绘制的电流，并向处理器报告由该处理器绘制的电流值处理器。报告的电流值实际上与实际绘制的电流的测量误差大于实际绘制的电流值。

6. 发明授权

US06772295B2 System and method for managing data in an I/O cache 失效
标题翻译：用于管理I / O缓存中的数据的系统和方法
公开(公告)号：US06772295B2
公开(公告)日：2004-08-03
申请号：US10322222
申请日：2002-12-17
申请人： Thomas V. Spencer , Robert J. Horning
发明人： Thomas V. Spencer , Robert J. Horning
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F12/0862 , G06F2212/6028
摘要： The present invention is generally directed to a system and method for fetching data from system memory to a device in communication with the system over a PCI bus, via an I/O cache. Broadly, the present invention may be viewed as a novel way to communicate certain fetching hints; namely, hints that specify certain qualities about the data that is to be fetched from the system memory. In operation, the I/O cache may use such hints to more effectively manage the data that passes through it. As simply one example, if, based upon the hints, the controller for the I/O cache knew (or assumed) that the data being fetched was ATM data, then it would also know (based upon the nature of ATM data) that precisely a forty-eight byte data payload was to be sent to the requesting device, and the I/O cache could pre-fetch precisely this amount of data (typically one or two cache lines). In accordance with one-aspect of the invention, such a system includes an input/output (I/O) cache memory interposed between the system memory and the PCI bus, wherein the cache memory has internal memory space in the form of a plurality of data lines within the cache memory. The system further includes a plurality of registers for each PCI master that are configured to define fetching criteria. Finally, the system includes a register selector that is configured to select an active register among the plurality of registers, wherein fetching criteria for the device is specified by the active register.
摘要翻译：本发明一般涉及一种系统和方法，用于经由I / O高速缓存将数据从系统存储器提取到与PCI总线通信的设备。概括地说，本发明可以被看作是传达某些提取提示的新颖方式; 即指定要从系统内存中提取的数据的某些质量的提示。在操作中，I / O缓存可以使用这样的提示来更有效地管理通过它的数据。作为一个例子，如果基于提示，I / O缓存的控制器知道（或假设）所取出的数据是ATM数据，则它也将精确地知道（基于ATM数据的性质），将48个字节的数据有效载荷发送到请求设备，并且I / O缓存可以精确地预取这一数量的数据（通常为一个或两个高速缓存行）。根据本发明的一个方面，这种系统包括插入在系统存储器和PCI总线之间的输入/输出（I / O）高速缓冲存储器，其中高速缓冲存储器具有多个形式的内部存储器空间高速缓存中的数据线。该系统还包括用于每个PCI主机的多个寄存器，其被配置为定义提取准则。最后，该系统包括一个寄存器选择器，被配置为在多个寄存器中选择一个活动寄存器，其中由该寄存器指定该设备的取得标准。

7. 发明授权

US06465121B1 Method for distributing electrolyte in batteries 失效
标题翻译：在电池中分配电解液的方法
公开(公告)号：US06465121B1
公开(公告)日：2002-10-15
申请号：US09652249
申请日：2000-08-30
申请人： Lev M. Dawson , Tracy E. Kelley , Oliver J. Gross , Robert J. Horning , Porter H. Mitchell
发明人： Lev M. Dawson , Tracy E. Kelley , Oliver J. Gross , Robert J. Horning , Porter H. Mitchell
IPC分类号： H01M238
CPC分类号： H01M2/38 , H01M2/0275 , H01M2/36 , H01M6/38 , H01M10/04 , H01M10/0436 , H01M10/0525 , H01M10/4214
摘要： A method for activating electrochemical cells including the steps of sealing the electrochemical cells in a container with an activating electrolyte solvent and salt, treatment steps, such as the application of compression and decompression cycles to the container, for providing good distribution of the electrolyte within the electrochemical cells.
摘要翻译：一种激活电化学电池的方法，包括用活化电解质溶剂和盐密封容器中的电化学电池的步骤，处理步骤，例如向容器施加压缩和减压循环，以提供电解质在该容器内的良好分布电化学电池。

8. 发明授权

US06457105B1 System and method for managing data in an asynchronous I/O cache memory 有权
标题翻译：用于管理异步I / O高速缓冲存储器中的数据的系统和方法
公开(公告)号：US06457105B1
公开(公告)日：2002-09-24
申请号：US09232505
申请日：1999-01-15
申请人： Thomas V Spencer , Robert J Horning
发明人： Thomas V Spencer , Robert J Horning
IPC分类号： G06F1200
CPC分类号： G06F12/121 , G06F2212/303
摘要： The present invention is generally directed to a system and method for providing improved memory management in an asynchronous I/O cache memory. The method includes the steps of identifying a request for data from the system memory by a requesting device that is in communication with the system memory via an I/O bus. Then the method controls the communication of data from the system memory into the cache memory. The method further includes the step of communicating the data from the cache memory to the requesting device, and immediately after communicating the data to the requesting device, the method discards the data from the cache memory. In accordance with the preferred embodiment, the method flushes data from the I/O cache line at a time. Therefore, when a given cache line of data is flushed from the cache after the last data byte of the cache line is communicated out to the requesting device.
摘要翻译：本发明一般涉及用于在异步I / O高速缓冲存储器中提供改进的存储器管理的系统和方法。该方法包括以下步骤：通过经由I / O总线与系统存储器通信的请求设备来识别来自系统存储器的数据请求。然后，该方法控制从系统存储器到高速缓冲存储器的数据通信。该方法还包括将数据从高速缓冲存储器传送到请求设备，并且在将数据传送到请求设备之后立即将该数据从高速缓冲存储器中丢弃的步骤。根据优选实施例，该方法一次从I / O高速缓存行刷新数据。因此，当在高速缓存行的最后一个数据字节被传送到请求设备之后，从缓存中刷新给定的高速缓存行数据时。

9. 发明授权

US06279081B1 System and method for performing memory fetches for an ATM card 有权
标题翻译：用于执行ATM卡的存储器提取的系统和方法
公开(公告)号：US06279081B1
公开(公告)日：2001-08-21
申请号：US09218226
申请日：1998-12-22
申请人： Thomas V Spencer , Robert J Horning , Monish S Shah
发明人： Thomas V Spencer , Robert J Horning , Monish S Shah
IPC分类号： G06F1200
CPC分类号： G06F12/0862
摘要： The present invention is generally directed to a system and method for fetching data from a system memory to an ATM card. The method includes the steps of receiving a request (via a PCI bus) to fetch data from memory, and identifying the request as an ATM request. The method then determines, based on the start address, the number of cache lines that will be implicated by the fetch. Then, the method automatically fetches the appropriate number of cache lines into the cache, and then passes the data to the ATM card, via the PCI bus. In accordance with another aspect of the present invention, a system is provided for fetching data from memory for an ATM card. Broadly, the system includes a system memory for data storage and a cache memory for providing high-speed (retrieval) temporary storage of data, the cache memory being disposed in communication with the system memory via a high-speed system bus. The system further includes a PCI bus in communication with the cache memory via an input/output (I/O) bus. A first mechanism is configured to identify a fetch for data from memory to the PCI bus by an ATM card. A second mechanism is configured to determine the number of lines of the cache memory that will be implicated by the identified fetch. Finally, a third mechanism is configured to automatically fetch the appropriate number of lines from the cache memory and to pass the data to the PCI bus.
摘要翻译：本发明一般涉及一种从系统存储器向ATM卡取出数据的系统和方法。该方法包括以下步骤：通过PCI总线接收从存储器提取数据的请求，并将该请求识别为ATM请求。然后，该方法基于开始地址确定将由提取涉及的高速缓存行的数量。然后，该方法自动将适当数量的高速缓存行提取到高速缓存中，然后通过PCI总线将数据传递到ATM卡。根据本发明的另一方面，提供一种用于从ATM卡的存储器取出数据的系统。广泛地说，该系统包括用于数据存储的系统存储器和用于提供数据的高速（检索）临时存储的高速缓冲存储器，该高速缓冲存储器经由高速系统总线被布置为与系统存储器通信。该系统还包括经由输入/输出（I / O）总线与高速缓冲存储器通信的PCI总线。第一机制被配置为通过ATM卡识别从存储器到PCI总线的数据的提取。第二机制被配置为确定将被识别的提取涉及的高速缓冲存储器的行数。最后，第三种机制被配置为从高速缓冲存储器自动获取适当数量的行并将数据传递到PCI总线。

10. 发明授权

US4433036A Multicell reserve battery 失效
标题翻译：多芯储存电池
公开(公告)号：US4433036A
公开(公告)日：1984-02-21
申请号：US364105
申请日：1982-03-31
申请人： Robert J. Horning , William J. Eppley
发明人： Robert J. Horning , William J. Eppley
IPC分类号： H01M6/38 , H01M6/36
CPC分类号： H01M6/38
摘要： A reserve battery having a plurality of galvanic cells and a series of ports through which electrolyte can flow into the cells. A spring activated valve opens the ports during periods of angular acceleration of the battery and closes the ports when there is no acceleration.
摘要翻译：一种备用电池，具有多个电池单元和一系列端口，电解液可以通过这些端口流入电池。弹簧启动阀在电池角加速期间打开端口，并且当没有加速时关闭端口。

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