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1. 发明授权

US08645673B2 Multicore processor and method of use that adapts core functions based on workload execution 失效
标题翻译：基于工作负载执行的多核处理器和使用方法可以调整核心功能
公开(公告)号：US08645673B2
公开(公告)日：2014-02-04
申请号：US13613936
申请日：2012-09-13
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00 , G06F9/06 , G06F9/24
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

2. 发明授权

US08327126B2 Multicore processor and method of use that adapts core functions based on workload execution 有权
标题翻译：基于工作负载执行的多核处理器和使用方法可以调整核心功能
公开(公告)号：US08327126B2
公开(公告)日：2012-12-04
申请号：US12197357
申请日：2008-08-25
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Glenn G. Daves , Ronald Edward Newhart , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/00 , G06F9/22 , G06F9/24 , G06F9/46
CPC分类号： G06F15/7871
摘要： A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.
摘要翻译：处理器具有多个核心，每个核心具有相关功能以支持处理器操作。通过平衡应用于每个功能的资源，选择性地改变由核执行的功能以改善处理器操作。例如，每个核心包括一个现场可编程阵列，该阵列可以根据使用每个功能的操作次数，选择性地和动态地编程来执行诸如浮点函数或固定点功能的功能。作为另一示例，处理器被构建为具有比可以同时供电的更多数量的核，每个核与功能相关联，使得具有较低利用率的功能的核被选择性地关机。

3. 发明授权

US07996346B2 Method for autonomic workload distribution on a multicore processor 有权
标题翻译：多核处理器上自主工作量分配的方法
公开(公告)号：US07996346B2
公开(公告)日：2011-08-09
申请号：US11959520
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Thomas Edward Cook , Thomas J. Dewkett , Naresh Nayar , Ronald Edward Newhart , Bernadette Ann Pierson , Michael Jay Shapiro
IPC分类号： G06F15/18 , G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5083
摘要： A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.
摘要翻译：一个包含自动工作负载分配的多处理器系统。当线程在多处理器系统中执行时，操作系统或管理程序将持续学习线程的执行特性，并将信息保存在线程特定的控制块中。执行特性用于生成线程性能数据。当线程执行时，操作系统会持续使用性能数据来将线程引导到最高效执行工作负载的内核。

4. 发明授权

US08495636B2 Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution 有权
标题翻译：通过对单线程程序执行前瞻性操作来在执行之前识别多条指令线程来并行化单线程程序
公开(公告)号：US08495636B2
公开(公告)日：2013-07-23
申请号：US11959906
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

5. 发明授权

US08544006B2 Resolving conflicts by restarting execution of failed discretely executable subcomponent using register and memory values generated by main component after the occurrence of a conflict 有权
标题翻译：通过在发生冲突后由主要组件生成的寄存器和内存值重新启动失败的离散可执行子组件的执行来解决冲突
公开(公告)号：US08544006B2
公开(公告)日：2013-09-24
申请号：US11959821
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/505 , G06F2209/5017
摘要： A method and apparatus for speculatively executing a single threaded program within a multi-core processor which includes identifying an idle core within the multi-core processor, performing a look ahead operation on the single thread instructions to identify speculative instructions within the single thread instructions, and allocating the idle core to execute the speculative instructions.
摘要翻译：一种用于在多核处理器内推测地执行单线程程序的方法和装置，其包括识别所述多核处理器内的空闲核心，对所述单线程指令执行向前操作以识别所述单线程指令内的推测指令，并分配空闲核心以执行推测性指令。

6. 发明授权

US08312455B2 Optimizing execution of single-threaded programs on a multiprocessor managed by compilation 有权
标题翻译：在编译器管理的多处理器上优化单线程程序的执行
公开(公告)号：US08312455B2
公开(公告)日：2012-11-13
申请号：US11960021
申请日：2007-12-19
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael A. Paolini , Michael Jay Shapiro
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A method for optimizing execution of a single threaded program on a multi-core processor. The method includes dividing the single threaded program into a plurality of discretely executable components while compiling the single threaded program; identifying at least some of the plurality of discretely executable components for execution by an idle core within the multi-core processor; and enabling execution of the at least one of the plurality of discretely executable components on the idle core.
摘要翻译：一种用于优化多核处理器上单个线程程序的执行的方法。该方法包括在编译单线程程序时将单线程程序划分成多个可离散执行的组件; 识别所述多个离散可执行部件中的至少一些，以供所述多核处理器内的空闲核心执行; 以及允许在所述空闲核心上执行所述多个离散可执行组件中的至少一个。

7. 发明授权

US08379847B2 Data and control encryption 有权
标题翻译：数据和控制加密
公开(公告)号：US08379847B2
公开(公告)日：2013-02-19
申请号：US12828080
申请日：2010-06-30
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael Jay Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Michael Jay Shapiro
IPC分类号： H04L9/00 , H04L9/32
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译：设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据由密钥定义的加密顺序。加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。

8. 发明授权

US09881099B2 System, method and computer program product for data transfer management 有权
公开(公告)号：US09881099B2
公开(公告)日：2018-01-30
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
IPC分类号： G06F17/30 , G06F12/00 , G06K9/62
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

9. 发明授权

US09582284B2 Performance of processors is improved by limiting number of branch prediction levels 有权
标题翻译：通过限制分支预测级别的数量来提高处理器的性能
公开(公告)号：US09582284B2
公开(公告)日：2017-02-28
申请号：US13308696
申请日：2011-12-01
申请人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
发明人： Robert H. Bell, Jr. , Wen-Tzer T. Chen
IPC分类号： G06F9/38 , G06F11/30
CPC分类号： G06F9/3844 , G06F9/3842 , G06F11/30 , G06F11/3024 , G06F11/3409 , G06F2201/81
摘要： A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread) for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribed threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold.
摘要翻译：一种方法利用由性能监视硬件提供的信息来动态调整对于处理器核心允许的推测分支预测级别（通常为每线程3或4个）。该信息包括处理器核心的每个指令周期（CPI）和每单位时间的存储器访问次数。如果CPI低于CPI阈值; 并且每单位时间的存储器访问次数（NMA）高于规定的阈值，则对于处理器核，每个线程的推测分支预测的级别数量减少。同样地，如果超过CPI阈值或每单位时间的存储器访问次数低于规定的阈值，则可以将推测分支预测的级数从低级别增加到允许的最大级别。

10. 发明授权

US09298458B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
公开(公告)号：US09298458B2
公开(公告)日：2016-03-29
申请号：US13427083
申请日：2012-03-22
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

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